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from 4770e3f8d89 [gn build] Add build file for llvm-pdbutil new 046371adb09 [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREM new cfa2cf74cd9 [X86][SSE] Don't use 'sign bit select' vXi8 ROTL lowering f [...]
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Summary of changes: lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 18 +- lib/Target/Mips/MipsInstructionSelector.cpp | 27 + lib/Target/Mips/MipsLegalizerInfo.cpp | 6 + lib/Target/Mips/MipsRegisterBankInfo.cpp | 4 + lib/Target/X86/X86ISelLowering.cpp | 7 +- .../GlobalISel/instruction-select/rem_and_div.mir | 110 ++++ .../Mips/GlobalISel/legalizer/rem_and_div.mir | 554 +++++++++++++++++++++ .../CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll | 314 ++++++++++++ .../Mips/GlobalISel/regbankselect/rem_and_div.mir | 102 ++++ test/CodeGen/X86/vector-fshl-rot-512.ll | 124 ++--- test/CodeGen/X86/vector-fshr-rot-512.ll | 132 ++--- test/CodeGen/X86/vector-rotate-128.ll | 323 +++++------- test/CodeGen/X86/vector-rotate-256.ll | 174 +++---- test/CodeGen/X86/vector-rotate-512.ll | 122 ++--- 14 files changed, 1452 insertions(+), 565 deletions(-) create mode 100644 test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir create mode 100644 test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir create mode 100644 test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll create mode 100644 test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir