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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug in repository toolchain/ci/gcc.
from 3bcaf16edd8 contrib/gcc-changelog: Skip over review lines adds 29c34351be8 git_commit.py: Add tests for signatures. adds d91524d5b11 [ARM]: Fix the wrong code-gen generated by MVE vector load/ [...]
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Summary of changes: contrib/ChangeLog | 6 + contrib/gcc-changelog/git_commit.py | 4 +- contrib/gcc-changelog/test_email.py | 5 + contrib/gcc-changelog/test_patches.txt | 34 +++++ gcc/ChangeLog | 52 +++++++ gcc/config/arm/arm-protos.h | 3 + gcc/config/arm/arm.c | 100 +++++++++++-- gcc/config/arm/arm.h | 8 +- gcc/config/arm/constraints.md | 23 ++- gcc/config/arm/mve.md | 156 ++++++++++++++------- gcc/config/arm/predicates.md | 6 + .../arm/mve/intrinsics/mve_vector_float2.c | 13 +- .../gcc.target/arm/mve/intrinsics/mve_vldr.c | 61 ++++++++ .../gcc.target/arm/mve/intrinsics/mve_vldr_z.c | 73 ++++++++++ .../gcc.target/arm/mve/intrinsics/mve_vstr.c | 43 ++++++ .../gcc.target/arm/mve/intrinsics/mve_vstr_p.c | 42 ++++++ .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 5 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 6 +- .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 6 +- .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 4 +- .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 5 +- .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 5 +- .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 6 +- .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 6 +- .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 3 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 5 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 5 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 5 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 5 +- .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 4 +- .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 4 +- .../arm/mve/intrinsics/vuninitializedq_float.c | 6 +- .../arm/mve/intrinsics/vuninitializedq_float1.c | 6 +- .../arm/mve/intrinsics/vuninitializedq_int.c | 8 +- .../arm/mve/intrinsics/vuninitializedq_int1.c | 8 +- 66 files changed, 692 insertions(+), 175 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vldr_z.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vstr_p.c