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from f289749578d tree-ssa-math-opts: correct -ffp-contract= check new c8da62cfc64 i386: Fix up types in __builtin_{inf,huge_val,nan{,s},fabs, [...] new ba490492e51 libstdc++: Implement LWG 3877 for std::expected monadic ops new 98827c53ed3 libstdc++: Add system_header pragma to <bits/c++config.h> new 6da6ed95c9c RISC-V: Remove masking third operand of rotate instructions new 5e1e16d58ec libstdc++: Uncomment checks for <limits> enumeration types
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Summary of changes: gcc/config/i386/i386-builtin-types.def | 2 +- gcc/config/riscv/bitmanip.md | 36 +++++++ gcc/config/riscv/iterators.md | 8 +- gcc/config/riscv/predicates.md | 10 +- gcc/config/riscv/riscv.md | 113 +++------------------ gcc/testsuite/c-c++-common/pr109884.c | 32 ++++++ gcc/testsuite/gcc.target/riscv/shift-and-2.c | 6 +- gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c | 3 +- gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c | 3 +- gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 3 +- gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c | 1 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c | 1 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c | 1 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c | 1 + libstdc++-v3/include/bits/c++config | 2 + libstdc++-v3/include/std/expected | 48 ++++----- .../18_support/headers/limits/synopsis.cc | 2 - libstdc++-v3/testsuite/20_util/expected/lwg3877.cc | 64 ++++++++++++ 18 files changed, 198 insertions(+), 138 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/pr109884.c create mode 100644 libstdc++-v3/testsuite/20_util/expected/lwg3877.cc