[Tcwg-commits] [toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (33203b4c27d -> 4e3d3e40726)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/gcc.

from 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation

No new revisions were added by this update.

Summary of changes: gcc/ChangeLog | 645 ++++ gcc/DATESTAMP | 2 +- gcc/asan.c | 5 +- gcc/c/ChangeLog | 17 + gcc/c/c-decl.c | 50 +- gcc/c/c-tree.h | 12 +- gcc/c/c-typeck.c | 3 +- gcc/config/aarch64/iterators.md | 3 +- gcc/config/arm/arm-builtins.c | 90 + gcc/config/arm/arm_mve.h | 3658 ++++++++++++++++---- gcc/config/arm/arm_mve_builtins.def | 96 + gcc/config/arm/mve.md | 1191 ++++++- gcc/cp/ChangeLog | 25 +- gcc/cp/constraint.cc | 2 +- gcc/cp/decl.c | 9 + gcc/cp/parser.c | 52 +- gcc/dwarf2out.c | 70 +- gcc/fold-const.c | 7 +- gcc/gimple-fold.c | 4 +- gcc/testsuite/ChangeLog | 223 ++ .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 5 +- .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 23 + .../intrinsics/{vrshrq_n_s16.c => vbicq_n_s16.c} | 12 +- .../intrinsics/{vrshrq_n_s32.c => vbicq_n_s32.c} | 12 +- .../intrinsics/{vrshrq_n_u16.c => vbicq_n_u16.c} | 12 +- .../intrinsics/{vrshrq_n_u32.c => vbicq_n_u32.c} | 12 +- .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 14 + 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.../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_p8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 22 + .../intrinsics/{vrshrq_n_s16.c => vorrq_n_s16.c} | 12 +- .../intrinsics/{vrshrq_n_s32.c => vorrq_n_s32.c} | 12 +- .../intrinsics/{vrshrq_n_u16.c => vorrq_n_u16.c} | 12 +- .../intrinsics/{vrshrq_n_u32.c => vorrq_n_u32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 2 +- .../{vhsubq_n_s16.c => vqdmullbq_n_s16.c} | 12 +- .../{vqaddq_n_s32.c => vqdmullbq_n_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 22 + .../{vhsubq_n_s16.c => vqdmulltq_n_s16.c} | 12 +- .../{vqaddq_n_s32.c => vqdmulltq_n_s32.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 22 + 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+- .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 2 +- .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + .../intrinsics/{vrshrq_n_s16.c => vshllbq_n_s16.c} | 12 +- .../intrinsics/{vrshrq_n_s8.c => vshllbq_n_s8.c} | 12 +- .../intrinsics/{vrshrq_n_u16.c => vshllbq_n_u16.c} | 12 +- .../intrinsics/{vrshrq_n_u8.c => vshllbq_n_u8.c} | 12 +- .../intrinsics/{vrshrq_n_s16.c => vshlltq_n_s16.c} | 12 +- .../intrinsics/{vrshrq_n_s8.c => vshlltq_n_s8.c} | 12 +- .../intrinsics/{vrshrq_n_u16.c => vshlltq_n_u16.c} | 12 +- .../intrinsics/{vrshrq_n_u8.c => vshlltq_n_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 3 +- .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 3 +- gcc/tree-ssa-dom.c | 9 +- gcc/tree-ssa-forwprop.c | 11 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-strlen.c | 3 +- libstdc++-v3/ChangeLog | 24 + libstdc++-v3/include/experimental/executor | 226 +- libstdc++-v3/include/experimental/socket | 18 +- .../testsuite/experimental/net/executor/1.cc | 93 + 272 files changed, 9443 insertions(+), 1035 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 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