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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project.
from 5fa2022ec00 [X86] Remove X86ISD::FILD_FLAG and stop gluing nodes together. adds 26ba1f77b55 [DebugInfo][test] Change two MIR tests to use -start-before [...] adds a72d15e37c5 [XRay] Set hasSideEffects flag of PATCHABLE_FUNCTION_{ENTER,EXIT} adds 9a24488cb67 [CodeGen] Move fentry-insert, xray-instrumentation and patc [...] adds 46be1689770 fix doc typos to cycle bots adds 4612e48d2fd [gn build] Port a0f50d73163 adds d82adf328fb Allow space after C-style cast in C# code adds 14c044756e7 [clang-format] Add IndentCaseBlocks option adds ea2be452542 [clang-format] Expand the SpacesAroundConditions option to [...] adds badc7e6cf9f Remove extra "\01" prefix in EH docs adds 70b53a30188 Fix gcc `-Wunused-variable` warning. NFC. adds 84217ad6611 [ORC] Add weak symbol support to defineMaterializing, fix f [...] adds 8e8a75ad508 [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true adds a7818e6f29c fix doc typos to cycle bots adds 886d2c2ca75 [BranchRelaxation] Simplify offset computation and fix a bu [...] adds 0ee1db2d1d7 [X86] Try to avoid casts around logical vector ops recursively. adds 819421745c5 Reorder targets in alphabetical order. NFC. adds 13fa4e2e5ae PR42108 Consistently diagnose binding a reference template [...] adds add2b7e44ad List implicit operator== after implicit destructors in a vtable. adds 7a9fa76be74 Undo changes to release notes intended for the Clang 10 bra [...] adds d15fad2653d [libc++][libc++abi] Fix or suppress failing tests in single [...] adds fc817b09e25 [mlir] NFC: Fix trivial typos in comments adds eaab1bf21e1 [StackColoring] Remap FixedStackPseudoSourceValue frame ind [...] new 5e51f755421 [ARM] Favour post inc for MVE loops new d6075726b90 [ARM] MVE VLDn post inc tests. NFC new ff2e67a4f70 [ARM] MVE VLDn postinc
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Summary of changes: clang/docs/ClangFormatStyleOptions.rst | 35 +- clang/docs/ReleaseNotes.rst | 43 +- clang/docs/SanitizerCoverage.rst | 4 +- clang/docs/analyzer/checkers.rst | 4 +- clang/include/clang/Format/Format.h | 26 +- clang/lib/AST/VTableBuilder.cpp | 46 +- clang/lib/Format/Format.cpp | 2 + clang/lib/Format/TokenAnnotator.cpp | 7 +- clang/lib/Format/UnwrappedLineParser.cpp | 3 +- clang/lib/Sema/SemaExprCXX.cpp | 12 +- clang/lib/Sema/SemaTemplate.cpp | 2 +- clang/lib/Serialization/ASTReaderStmt.cpp | 6 +- clang/test/CodeGenCXX/virtual-compare.cpp | 53 ++ clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp | 14 + clang/unittests/Format/FormatTest.cpp | 54 ++ clang/unittests/Format/FormatTestCSharp.cpp | 9 + .../test/libcxx/modules/cinttypes_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/clocale_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/cstdint_exports.sh.cpp | 4 + .../test/libcxx/modules/inttypes_h_exports.sh.cpp | 4 + libcxx/test/libcxx/modules/stdint_h_exports.sh.cpp | 4 + libcxxabi/test/guard_test_basic.pass.cpp | 2 +- llvm/docs/ExceptionHandling.rst | 14 +- llvm/include/llvm/CodeGen/PseudoSourceValue.h | 3 +- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 2 +- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 13 +- llvm/include/llvm/IR/IntrinsicsARM.td | 9 +- llvm/include/llvm/Target/Target.td | 4 +- llvm/lib/CodeGen/BranchRelaxation.cpp | 13 +- llvm/lib/CodeGen/StackColoring.cpp | 9 + llvm/lib/CodeGen/TargetPassConfig.cpp | 12 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 77 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 4 +- .../Orc/RTDyldObjectLinkingLayer.cpp | 43 +- llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp | 3 - llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 4 - llvm/lib/Target/AMDGPU/R600RegisterInfo.h | 4 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 5 - llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 1 - llvm/lib/Target/ARC/ARCRegisterInfo.cpp | 5 - llvm/lib/Target/ARC/ARCRegisterInfo.h | 2 - llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 5 - llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 2 - llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 144 ++-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 159 ++++- llvm/lib/Target/ARM/ARMInstrMVE.td | 38 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 14 + llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 7 +- llvm/lib/Target/AVR/AVRRegisterInfo.h | 4 - llvm/lib/Target/Hexagon/HexagonRegisterInfo.h | 4 - llvm/lib/Target/LLVMBuild.txt | 8 +- llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp | 5 - llvm/lib/Target/Lanai/LanaiRegisterInfo.h | 2 - llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 5 - llvm/lib/Target/Mips/MipsRegisterInfo.h | 2 - llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 4 - llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 4 - llvm/lib/Target/SystemZ/SystemZRegisterInfo.h | 3 - llvm/lib/Target/X86/X86ISelLowering.cpp | 103 +-- llvm/lib/Target/X86/X86RegisterInfo.cpp | 6 - llvm/lib/Target/X86/X86RegisterInfo.h | 4 - llvm/lib/Target/XCore/XCoreRegisterInfo.cpp | 5 - llvm/lib/Target/XCore/XCoreRegisterInfo.h | 2 - llvm/test/CodeGen/AArch64/O0-pipeline.ll | 6 +- llvm/test/CodeGen/AArch64/O3-pipeline.ll | 6 +- llvm/test/CodeGen/AArch64/branch-relax-bcc.ll | 12 +- .../AArch64/patchable-function-entry-bti.ll | 24 + llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 3 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 6 +- .../test/CodeGen/PowerPC/stack-coloring-vararg.mir | 192 +++++ .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 34 +- .../Thumb2/LowOverheadLoops/mve-float-loops.ll | 634 ++++++++--------- .../Thumb2/LowOverheadLoops/mve-tail-data-types.ll | 393 +++++------ .../LowOverheadLoops/vector-arith-codegen.ll | 17 +- llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll | 6 +- llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll | 91 +++ llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll | 11 +- llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll | 66 +- llvm/test/CodeGen/Thumb2/mve-vld2-post.ll | 168 +++++ llvm/test/CodeGen/Thumb2/mve-vld2.ll | 78 +-- llvm/test/CodeGen/Thumb2/mve-vld4-post.ll | 272 ++++++++ llvm/test/CodeGen/Thumb2/mve-vld4.ll | 412 +++++------ llvm/test/CodeGen/Thumb2/mve-vldst4.ll | 278 ++++---- llvm/test/CodeGen/Thumb2/mve-vmla.ll | 24 +- llvm/test/CodeGen/Thumb2/mve-vst2-post.ll | 165 +++++ llvm/test/CodeGen/Thumb2/mve-vst2.ll | 58 +- llvm/test/CodeGen/Thumb2/mve-vst4-post.ll | 250 +++++++ llvm/test/CodeGen/Thumb2/mve-vst4.ll | 208 +++--- llvm/test/CodeGen/X86/O0-pipeline.ll | 6 +- llvm/test/CodeGen/X86/O3-pipeline.ll | 6 +- llvm/test/CodeGen/X86/v8i1-masks.ll | 774 ++++++--------------- llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir | 4 +- llvm/test/DebugInfo/X86/debug-loc-asan.mir | 4 +- llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn | 1 + mlir/docs/ConversionToLLVMDialect.md | 2 +- mlir/docs/Dialects/Vector.md | 2 +- mlir/docs/ShapeInference.md | 2 +- mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 7 +- mlir/include/mlir/Dialect/LoopOps/LoopOps.td | 4 +- mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 6 +- mlir/include/mlir/IR/StandardTypes.h | 2 +- mlir/include/mlir/Support/STLExtras.h | 5 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 2 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp | 4 +- mlir/lib/Dialect/VectorOps/VectorTransforms.cpp | 6 +- mlir/lib/IR/AsmPrinter.cpp | 2 +- mlir/lib/IR/StandardTypes.cpp | 2 +- mlir/lib/IR/Visitors.cpp | 2 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 2 +- mlir/lib/Transforms/LoopFusion.cpp | 2 +- mlir/test/Dialect/SPIRV/target-env.mlir | 2 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 2 +- mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 6 +- mlir/tools/mlir-tblgen/RewriterGen.cpp | 2 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 2 +- 116 files changed, 3243 insertions(+), 2133 deletions(-) create mode 100644 clang/test/CodeGenCXX/virtual-compare.cpp create mode 100644 llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll create mode 100644 llvm/test/CodeGen/PowerPC/stack-coloring-vararg.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-vld2-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vld4-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vst2-post.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vst4-post.ll