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from 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] new 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. new 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...]
The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/ChangeLog | 357 +++++ gcc/config/arm/arm-builtins.c | 7 + gcc/config/arm/arm_mve.h | 1613 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 12 + gcc/config/arm/mve.md | 373 ++++- gcc/testsuite/ChangeLog | 74 + .../intrinsics/{vclzq_m_u16.c => vddupq_m_n_u16.c} | 11 +- .../{vdupq_m_n_u32.c => vddupq_m_n_u32.c} | 7 +- .../intrinsics/{vdupq_m_n_u8.c => vddupq_m_n_u8.c} | 11 +- .../{vclzq_m_u16.c => vddupq_m_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => vddupq_m_wb_u32.c} | 11 +- .../{vdupq_m_n_u8.c => vddupq_m_wb_u8.c} | 11 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vddupq_n_u8.c} | 12 +- .../intrinsics/{vmovlbq_u8.c => vddupq_wb_u16.c} | 12 +- .../intrinsics/{vmovlbq_u16.c => vddupq_wb_u32.c} | 12 +- .../intrinsics/{vqshluq_n_s8.c => vddupq_wb_u8.c} | 12 +- .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../{vqrshlq_m_n_u16.c => vdwdupq_m_wb_u16.c} | 11 +- .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../intrinsics/{vclzq_m_u16.c => vidupq_m_n_u16.c} | 11 +- .../{vdupq_m_n_u32.c => vidupq_m_n_u32.c} | 7 +- .../intrinsics/{vdupq_m_n_u8.c => vidupq_m_n_u8.c} | 11 +- .../{vclzq_m_u16.c => vidupq_m_wb_u16.c} | 11 +- .../{vclzq_m_u32.c => vidupq_m_wb_u32.c} | 11 +- .../{vdupq_m_n_u8.c => vidupq_m_wb_u8.c} | 11 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u16.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u32.c} | 12 +- .../mve/intrinsics/{vctp32q.c => vidupq_n_u8.c} | 12 +- .../intrinsics/{vmovlbq_u8.c => vidupq_wb_u16.c} | 12 +- .../intrinsics/{vmovlbq_u16.c => vidupq_wb_u32.c} | 12 +- .../intrinsics/{vqshluq_n_s8.c => vidupq_wb_u8.c} | 12 +- .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + 68 files changed, 3653 insertions(+), 134 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vddupq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u32.c => vddupq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vddupq_m_n_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vddupq_m_wb_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => vddupq_m_wb_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vddupq_m_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vddupq_n_u8.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u8.c => vddupq_wb_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u16.c => vddupq_wb_u32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqshluq_n_s8.c => vddupq_wb_u8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqrshlq_m_n_u16.c => vdwdupq_m_w [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vidupq_m_n_u16. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u32.c => vidupq_m_n_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vidupq_m_n_u8. [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u16.c => vidupq_m_wb_u16 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vclzq_m_u32.c => vidupq_m_wb_u32 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_m_n_u8.c => vidupq_m_wb_u8 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u16.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u32.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vctp32q.c => vidupq_n_u8.c} (55%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u8.c => vidupq_wb_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vmovlbq_u16.c => vidupq_wb_u32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vqshluq_n_s8.c => vidupq_wb_u8.c} (52%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c