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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allnoconfig in repository toolchain/ci/llvm-project.
from 43bbca92284 RewriteObjC - silence static analyzer getAs<> null derefere [...] adds 41c934acaf8 [SelectionDAG] Add tests for LKK algorithm adds 68f21b360b9 Try to fix sphinx indentation error adds 9ecacb0d54f [X86] lowerShuffleAsLanePermuteAndRepeatedMask - variable r [...] adds e2321bb4488 [SLP] avoid reduction transform on patterns that the backen [...] adds 8815be04ec1 [X86][AVX] Push sign extensions of comparison bool results [...] adds 2decdf42b95 [FastISel] Copy the inline assembly dialect to the INLINEAS [...] adds 69c65a86097 AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics adds a5b9c756745 GlobalISel: Partially implement lower for G_EXTRACT adds bcd6b1d2090 AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS adds c0ec72d4f85 AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics adds 786a3953bac AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics adds e59296a0519 AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets adds c209598268b [clang-format][docs] Fix the Google C++ and Chromium style [...] adds 7653ff398d2 [X86] Enable AVX512BW for memcmp() new 032dd9b086c [X86][SSE] matchVectorShuffleAsBlend - use Zeroable element [...] new c38881a6b7f [InstCombine] don't assume 'inbounds' for bitcast pointer t [...] new 61c22a83dee [InstCombine] add fast-math-flags for better test coverage; NFC new 2dee7e55610 [X86][AVX] combineExtractSubvector - merge duplicate variab [...]
The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang/docs/ClangFormatStyleOptions.rst | 2 +- clang/docs/ReleaseNotes.rst | 8 +- clang/test/CodeGen/aapcs-bitfield.c | 72 +- .../test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp | 16 +- clang/test/CodeGenCXX/microsoft-abi-typeid.cpp | 2 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 10 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + llvm/lib/Analysis/TargetTransformInfo.cpp | 53 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 35 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 1 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 17 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 48 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 177 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 11 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 15 +- llvm/test/CodeGen/AArch64/srem-lkk.ll | 149 ++ llvm/test/CodeGen/AArch64/srem-vector-lkk.ll | 324 ++++ llvm/test/CodeGen/AArch64/urem-lkk.ll | 103 ++ llvm/test/CodeGen/AArch64/urem-vector-lkk.ll | 267 ++++ .../GlobalISel/artifact-combiner-extract.mir | 14 +- .../legalize-atomic-cmpxchg-with-success.mir | 107 ++ .../GlobalISel/legalize-extract-vector-elt.mir | 20 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 183 ++- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 20 +- .../regbankselect-amdgcn.ds.gws.init.mir | 79 + .../regbankselect-amdgcn.ds.gws.sema.v.mir | 37 + .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 13 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 15 +- .../AMDGPU/GlobalISel/regbankselect-constant.mir | 8 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 149 ++ llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 1675 +++++++++++++++++++ llvm/test/CodeGen/PowerPC/urem-lkk.ll | 106 ++ llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll | 1338 ++++++++++++++++ llvm/test/CodeGen/RISCV/srem-lkk.ll | 583 +++++++ llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 1689 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/urem-lkk.ll | 354 ++++ llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 1419 ++++++++++++++++ llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 161 +- llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll | 124 +- llvm/test/CodeGen/X86/memcmp.ll | 20 +- llvm/test/CodeGen/X86/packss.ll | 22 +- llvm/test/CodeGen/X86/pr43575.ll | 14 + llvm/test/CodeGen/X86/setcc-wide-types.ll | 118 +- llvm/test/CodeGen/X86/srem-lkk.ll | 159 ++ llvm/test/CodeGen/X86/srem-vector-lkk.ll | 556 +++++++ llvm/test/CodeGen/X86/urem-lkk.ll | 108 ++ llvm/test/CodeGen/X86/urem-vector-lkk.ll | 378 +++++ llvm/test/Transforms/InstCombine/addrspacecast.ll | 2 +- llvm/test/Transforms/InstCombine/cast.ll | 4 +- llvm/test/Transforms/InstCombine/fmul.ll | 8 +- .../Transforms/InstCombine/load-bitcast-vec.ll | 35 + llvm/test/Transforms/InstCombine/memset.ll | 2 +- llvm/test/Transforms/InstCombine/unpack-fca.ll | 18 +- .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 156 +- 55 files changed, 10540 insertions(+), 472 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/srem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-wit [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/PowerPC/srem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/pr43575.ll create mode 100644 llvm/test/CodeGen/X86/srem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-vector-lkk.ll