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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-allnoconfig in repository toolchain/ci/llvm-project.
from 216200aff268 [libc++] Fix hang in counting_semaphore::try_acquire adds ed38280d006c [ARM] Use hardware TLS register in Thumb2 mode when -mtp=c [...] adds ff2cb6e400c3 [clang] Partially revert d8cd7806310c51af912a647a6ca46de62 [...] adds d5159b99105d MLIR can't support -Bsymbolic link option, fail at CMake t [...] adds 9e084f4194e6 Fix building with GCC 12: adds 8be24d19fefa [MergeICmps] Don't merge icmps derived from pointers with [...] adds 162f3f18c945 [Aarch64] Correct register class for pseudo instructions
No new revisions were added by this update.
Summary of changes: clang/lib/Basic/Targets/OSTargets.h | 4 +- clang/test/Preprocessor/init.c | 2 - .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 1 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 32 ++++---- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrThumb.td | 1 + llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 + llvm/lib/Transforms/Scalar/MergeICmps.cpp | 4 + .../CodeGen/AArch64/GlobalISel/select-add-low.mir | 4 +- .../AArch64/GlobalISel/select-blockaddress.mir | 5 +- .../AArch64/GlobalISel/select-gv-with-offset.mir | 2 +- .../select-jump-table-brjt-constrain.mir | 2 +- .../AArch64/GlobalISel/select-jump-table-brjt.mir | 2 +- .../CodeGen/AArch64/GlobalISel/select-static.mir | 4 +- llvm/test/CodeGen/AArch64/GlobalISel/select.mir | 8 +- llvm/test/CodeGen/AArch64/elim-dead-mi.mir | 10 +-- llvm/test/CodeGen/AArch64/loop-sink.mir | 6 +- llvm/test/CodeGen/ARM/readtp.ll | 2 + llvm/test/CodeGen/ARM/thread_pointer.ll | 8 +- .../Transforms/MergeICmps/X86/addressspaces.ll | 94 ++++++++++++++++++++++ mlir/CMakeLists.txt | 6 ++ 21 files changed, 157 insertions(+), 45 deletions(-) create mode 100644 llvm/test/Transforms/MergeICmps/X86/addressspaces.ll