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from 9ac8aecbf9d [RISCV] Allow conversion of CC logic to bitwise logic new d580c5bcede [RISCV] Optimize emission of SELECT sequences
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Summary of changes: lib/Target/RISCV/RISCVISelLowering.cpp | 107 ++++- test/CodeGen/RISCV/atomic-rmw.ll | 600 ++++++++---------------- test/CodeGen/RISCV/select-optimize-multiple.ll | 323 +++++++++++++ test/CodeGen/RISCV/select-optimize-multiple.mir | 191 ++++++++ 4 files changed, 804 insertions(+), 417 deletions(-) create mode 100644 test/CodeGen/RISCV/select-optimize-multiple.ll create mode 100644 test/CodeGen/RISCV/select-optimize-multiple.mir