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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allyesconfig in repository toolchain/ci/llvm-project.
from 0dc91bfd11e [mlir][spirv] Handle debuginfo for control flow ops. adds 42a9ca0245a [ARM] Extra VQMOVN/VQSHRN tests. NFC adds be6847b17d7 Fix -Wdocumentation warning. NFC. adds 43bf2be4d92 LLParser.cpp - remove headers explicitly included in LLPars [...] adds 25656332f18 AggressiveAntiDepBreaker.cpp - remove headers explicitly in [...] adds 228913780b6 DIEHash.cpp - remove headers explicitly included in DIEHash [...] adds 2e1fbf85b65 [ARM] MVE saturating truncates adds 72f1fb2edf5 [ARM] Combines for VMOVN adds 5be37cb124f [x86][CGP] try to hoist funnel shift above select-of-splats adds 9a05547954a [AArch64] Precommit tests for D77316 adds 6211830fbab [VectorCombine] add reduction-like patterns; NFC adds 2123bb843e4 [ARM] Patterns for VQSHRN adds 604f44977bd [InstCombine] Clean up alignment handling (NFC) adds 43017ceb784 [PhaseOrdering] add vector reduction tests; NFC adds 81e9ede3a2d [VectorCombine] forward walk through instructions to improv [...] adds 49c9a68d7fc The release notes for ObjCBreakBeforeNestedBlockParam was p [...] adds 32870a84d9a Expose IRGen API to add the default IR attributes to a func [...] adds 0ee46e857d8 [nfc] test commit adds accd9af838b Revert "[nfc] test commit" adds 0ec5f501964 Harden IR and bitcode parsers against infinite size types. adds 135b877874f [X86] Replace selectScalarSSELoad ComplexPattern with PatFr [...] adds 4f04db4b543 AllocaInst should store Align instead of MaybeAlign. adds 796ae8cf820 [LegalizeDAG] Use MachinePointerInfo::getUnknownStack in pl [...] adds bc98dc12d83 Try to heal bots after https://reviews.llvm.org/D79655 adds 3735505e4ff Fix a few doc typos to cycle bots. adds 2fe66bdb2e5 [Compiler-rt] Emit error if builtins library cannot be found
No new revisions were added by this update.
Summary of changes: clang/docs/ConstantInterpreter.rst | 4 +- clang/docs/ReleaseNotes.rst | 32 +- clang/include/clang/CodeGen/CodeGenABITypes.h | 20 + clang/lib/CodeGen/CGCall.cpp | 141 ++- clang/lib/CodeGen/CodeGenABITypes.cpp | 5 + clang/lib/CodeGen/CodeGenAction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.h | 17 +- clang/test/CodeGenCXX/wasm-eh.cpp | 6 + compiler-rt/cmake/Modules/AddCompilerRT.cmake | 3 + llvm/include/llvm/AsmParser/Parser.h | 1 - llvm/include/llvm/IR/Instructions.h | 26 +- .../llvm/Transforms/Scalar/MemCpyOptimizer.h | 2 +- llvm/lib/AsmParser/LLParser.cpp | 18 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 14 +- llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 5 - llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 2 - llvm/lib/CodeGen/CodeGenPrepare.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 8 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +- llvm/lib/IR/Core.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 37 +- llvm/lib/Target/AArch64/AArch64StackTagging.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 4 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 154 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 4 + llvm/lib/Target/ARM/ARMInstrMVE.td | 43 + llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp | 6 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 75 -- llvm/lib/Target/X86/X86InstrAVX512.td | 42 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 34 +- llvm/lib/Target/X86/X86InstrSSE.td | 46 +- llvm/lib/Target/X86/X86InstrXOP.td | 4 +- llvm/lib/Transforms/Coroutines/CoroElide.cpp | 10 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 2 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 7 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 5 +- llvm/lib/Transforms/IPO/Inliner.cpp | 2 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 48 +- .../Instrumentation/AddressSanitizer.cpp | 18 +- .../Instrumentation/HWAddressSanitizer.cpp | 4 +- llvm/lib/Transforms/Scalar/GVNHoist.cpp | 5 +- llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp | 16 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Utils/Local.cpp | 2 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 5 +- llvm/test/Assembler/alloca-addrspace-elems.ll | 6 +- llvm/test/Assembler/alloca-addrspace0.ll | 6 +- llvm/test/Assembler/block-labels.ll | 2 +- .../datalayout-alloca-addrspace-mismatch-0.ll | 2 +- llvm/test/Assembler/datalayout-alloca-addrspace.ll | 6 +- .../Assembler/drop-debug-info-nonzero-alloca.ll | 2 +- llvm/test/CodeGen/AArch64/shift-amount-mod.ll | 331 ++++++ llvm/test/CodeGen/AMDGPU/alloca.ll | 2 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 244 ++--- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll | 1092 +++++++++----------- llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll | 257 +++++ llvm/test/CodeGen/Thumb2/mve-vqmovn.ll | 40 +- .../Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} | 412 ++++---- llvm/test/CodeGen/X86/vector-fshl-256.ll | 84 +- llvm/test/Transforms/ArgumentPromotion/attrs.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval-2.ll | 14 +- llvm/test/Transforms/ArgumentPromotion/byval.ll | 20 +- llvm/test/Transforms/ArgumentPromotion/dbg.ll | 6 +- llvm/test/Transforms/ArgumentPromotion/tail.ll | 10 +- .../Attributor/ArgumentPromotion/attrs.ll | 22 +- .../Attributor/ArgumentPromotion/byval-2.ll | 10 +- .../Attributor/ArgumentPromotion/byval.ll | 88 +- .../Attributor/ArgumentPromotion/fp80.ll | 4 +- .../Attributor/ArgumentPromotion/inalloca.ll | 2 +- .../Attributor/ArgumentPromotion/tail.ll | 8 +- .../IPConstantProp/2009-09-24-byval-ptr.ll | 60 +- llvm/test/Transforms/Attributor/value-simplify.ll | 2 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 129 ++- llvm/test/Transforms/NewGVN/pr33367.ll | 2 +- .../PhaseOrdering/X86/vector-reductions.ll | 69 ++ llvm/test/Transforms/SROA/alignment.ll | 4 +- llvm/test/Transforms/SROA/pointer-offset-size.ll | 4 +- .../Transforms/VectorCombine/X86/extract-binop.ll | 61 ++ .../Transforms/VectorCombine/X86/insert-binop.ll | 8 +- llvm/test/Verifier/recursive-type-load.ll | 12 + llvm/test/Verifier/recursive-type-store.ll | 12 + mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 2 +- polly/lib/CodeGen/BlockGenerators.cpp | 5 +- polly/lib/CodeGen/IslNodeBuilder.cpp | 8 +- 87 files changed, 2458 insertions(+), 1541 deletions(-) create mode 100644 llvm/test/CodeGen/Thumb2/mve-vqmovn-combine.ll copy llvm/test/CodeGen/Thumb2/{mve-vqmovn.ll => mve-vqshrn.ll} (56%) create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll create mode 100644 llvm/test/Verifier/recursive-type-load.ll create mode 100644 llvm/test/Verifier/recursive-type-store.ll