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from d9a1d02 MCInstrDesc: Flags (uint64_t) was checked using (1 << MCID::X [...] new c71d5b4 [CodeGen] Split out the notions of MI invariance and MI deref [...] new 877859e [NVPTX] Use ldg for explicitly invariant loads. new 362611f Add handling of !invariant.load to PropagateMetadata.
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Summary of changes: include/llvm/CodeGen/MachineMemOperand.h | 13 ++++---- include/llvm/CodeGen/SelectionDAGNodes.h | 6 ++-- lib/Analysis/VectorUtils.cpp | 12 ++++---- lib/CodeGen/MIRParser/MILexer.cpp | 1 + lib/CodeGen/MIRParser/MILexer.h | 3 +- lib/CodeGen/MIRParser/MIParser.cpp | 3 ++ lib/CodeGen/MIRPrinter.cpp | 2 ++ lib/CodeGen/MachineInstr.cpp | 7 +++-- lib/CodeGen/MachinePipeliner.cpp | 3 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 ++ lib/CodeGen/SelectionDAG/FastISel.cpp | 4 +++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 6 ++-- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++-- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 18 ++++------- lib/Target/AArch64/AArch64ISelLowering.cpp | 11 +++---- lib/Target/AMDGPU/R600ISelLowering.cpp | 5 ++-- lib/Target/AMDGPU/SIISelLowering.cpp | 19 +++++++----- lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 ++- lib/Target/ARM/ARMISelLowering.cpp | 20 +++++++------ lib/Target/ARM/ARMInstrInfo.cpp | 4 ++- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 35 ++++++++++++++-------- lib/Target/NVPTX/NVPTXISelLowering.cpp | 9 ++++-- lib/Target/PowerPC/PPCISelLowering.cpp | 16 ++++------ lib/Target/PowerPC/PPCISelLowering.h | 14 ++++++++- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 2 +- lib/Target/X86/X86InstrInfo.cpp | 4 ++- test/CodeGen/NVPTX/ldg-invariant.ll | 27 +++++++++++++++++ .../NVPTX/propagate-invariance-metadata.ll | 17 +++++++++++ 28 files changed, 184 insertions(+), 89 deletions(-) create mode 100644 test/CodeGen/NVPTX/ldg-invariant.ll create mode 100644 test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance- [...]