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from b6a51390979 c: Correct type compatibility for bit-fields [PR117828] new 356bfe8ca12 RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod [...] new fe29b03825c RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/do [...]
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Summary of changes: gcc/config.gcc | 2 +- gcc/config/riscv/generic-vector-ooo.md | 2 +- gcc/config/riscv/genrvv-type-indexer.cc | 47 +++++ gcc/config/riscv/riscv-vector-builtins-shapes.cc | 30 +++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 2 + gcc/config/riscv/riscv-vector-builtins-types.def | 12 ++ gcc/config/riscv/riscv-vector-builtins.cc | 151 ++++++++++++++- gcc/config/riscv/riscv-vector-builtins.def | 26 ++- gcc/config/riscv/riscv-vector-builtins.h | 14 ++ gcc/config/riscv/riscv.md | 4 +- gcc/config/riscv/sifive-vector-builtins-bases.cc | 164 ++++++++++++++++ .../sifive-vector-builtins-bases.h} | 25 ++- .../riscv/sifive-vector-builtins-functions.def | 54 ++++++ gcc/config/riscv/sifive-vector.md | 164 ++++++++++++++++ gcc/config/riscv/t-riscv | 20 ++ gcc/config/riscv/vector-iterators.md | 32 ++++ gcc/config/riscv/vector.md | 1 + gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + .../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c | 213 +++++++++++++++++++++ .../riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c | 213 +++++++++++++++++++++ 26 files changed, 2428 insertions(+), 28 deletions(-) create mode 100644 gcc/config/riscv/sifive-vector-builtins-bases.cc copy gcc/config/{aarch64/aarch64-neon-sve-bridge-builtins.def => riscv/sifive-vect [...] create mode 100644 gcc/config/riscv/sifive-vector-builtins-functions.def create mode 100644 gcc/config/riscv/sifive-vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c