[Tcwg-commits] [toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_check/release-aarch64 updated (bf470982f9 -> d8c4766d31)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/release-aarch64 in repository toolchain/ci/binutils-gdb.

from bf470982f9 sim: enable -Werror by default for some arches adds 50df264dae sim: clean up stale AC_PREREQ refs adds f8cab0b995 sim: sh64: delete port adds f074c07d8d sim: common: clean up asprintf includes a bit adds 7eb99e5e27 sim: cr16/d10v: move storage out of header adds a9fd212a24 sim: replace rindex with strrchr adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB adds af019bfde9 Support the PGO build for binutils+gdb adds 66beed0227 Fix erroneous agent expression test adds bc167b6b3e Remove a use of print_expression adds 54585eee2e Avoid crash in compile_to_object adds 5834526f4b Automatic date update in version.in adds 46b1518d4c Automatic date update in version.in adds a8aa72b913 Updated translations for multiple subdirectories adds 68ed285428 sim: clean up C11 header includes adds 933306703a sim: rl78: move storage out of header adds 90e123dd60 sim: common: fix printf formats adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS adds c0f6e439cc Add support for more MIPS variants to the linker command line. adds 82c70b08df aarch64: Remove support for CSRE adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S adds 062eaacbac gdb: change jit_debug to a bool adds eef401dce1 gdb: convert solib-aix to new-style debug macros adds c6185dce03 gdb: convert aarch64 to new-style debug macros adds 254c3783fe sim: tests: get common tests working again adds eabdd87b2e Automatic date update in version.in adds 03c02f3116 GCC: Check if AR works with --plugin and rc adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc adds 44124a4683 binuitils: Check if AR is usable for LTO build adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call adds f220ef633c sim: common: use #error properly adds 68895f7d7e sim: README-HACKING: clean up stale run references adds 5e9e2f41eb sim: or1k: clean up stale build entries adds e998918e98 sim: or1k: fix mixing of code & decl warning adds 7c654b719d gdb/fortran: add symbol base comparison operators adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions adds 6d104cac0a Updated translations for some subdirectories adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...] adds d546b61084 Implement a workaround for GNU mak jobserver adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb. adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h adds 24a7f1b548 gdb: fix indentation in infrun.c adds 3034143dc6 src-release: fix indentation adds 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure adds 30845f113a PowerPC use_local_plt adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32 adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32 adds c98de297b3 libctf, ld: fix data symbol test with newer GCC adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...] adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame adds c65ca138c4 sim: ppc: update version script usage adds bdec2917b1 Convert some frame functions to use gdb::array_view. adds a9a87d3525 trad-frame cleanups adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis adds 11321a0505 Automatic date update in version.in adds 8bd10d6b16 PowerPC64 synthetic symbols adds 4bd7c90276 PowerPC: Don't generate unused section symbols adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32 adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...] adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32 adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32 adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...] adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...] adds 3f0781f389 Automatic date update in version.in adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name adds 6bd434d6ca gdb: make some variables static adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp adds d4dd4fca16 gdb: change debug_bfd_cache to bool adds c78eec4424 mips XPASS pr26936 adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel adds 7cb6d92a3f gdb: convert arm to new-style debug macros adds 325d39e4e0 Add Python support for hardware breakpoints adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp adds 439706e6a9 gdb: use interruptible_select when connecting to a remote adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c adds a59902a7c1 gdb: convert auto-load to new-style debug macros adds d5d24e12f9 Fix build errors for armhf adds cd211c75cb Handle additional connection error adds e534c7e8c4 Automatic date update in version.in adds c651f0a614 MAINTAINERS: Update my e-mail address adds cc4bc93e52 gdb/doc: down case contents of @var adds fe461d2f70 gdb/doc: move @menu to the end of the node adds 5b7d941b90 gdb: add owner-related methods to struct type adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro adds 344e9841d9 gdb: remove TYPE_OBJFILE macro adds baf2b57f18 gdb: move set remote commands to remote.c adds cda09ec9f9 gdb: move remote_debug to remote.{h,c} adds 02349803fc gdb: change remote_debug to bool adds 2189c31265 gdb: add remote_debug_printf adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs

No new revisions were added by this update.

Summary of changes: ChangeLog | 50 + Makefile.in | 68 +- Makefile.tpl | 63 +- bfd/ChangeLog | 133 + bfd/Makefile.in | 1 + bfd/aclocal.m4 | 1 + bfd/bfd-in2.h | 7 +- bfd/compress.c | 3 +- bfd/configure | 53 +- bfd/configure.ac | 2 + bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 5 +- bfd/elf32-bfin.c | 235 +- bfd/elf32-i386.c | 36 + bfd/elf32-ppc.c | 55 +- bfd/elf64-ppc.c | 83 +- bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 202 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/po/fr.po | 2666 +-- bfd/po/pt.po | 2681 +-- bfd/po/sr.po | 2687 ++-- bfd/po/uk.po | 2666 +-- bfd/reloc.c | 7 + bfd/section.c | 7 +- bfd/version.h | 2 +- binutils/ChangeLog | 57 + binutils/MAINTAINERS | 8 +- binutils/Makefile.in | 1 + binutils/aclocal.m4 | 1 + binutils/configure | 53 +- binutils/configure.ac | 2 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/po/fr.po | 3826 +++-- binutils/po/pt.po | 3943 ++--- binutils/po/sr.po | 3845 +++-- binutils/po/sv.po | 3804 +++-- binutils/po/uk.po | 3840 +++-- binutils/readelf.c | 8 +- config/ChangeLog | 15 + config/gcc-plugin.m4 | 40 + config/jobserver.m4 | 24 + configure | 246 +- configure.ac | 84 + gas/ChangeLog | 140 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/NEWS | 8 +- gas/aclocal.m4 | 1 + gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 4 - gas/config/tc-aarch64.c | 31 - gas/config/tc-i386.c | 42 +- gas/config/tc-riscv.c | 521 +- gas/config/tc-riscv.h | 6 +- gas/configure | 53 +- gas/configure.ac | 2 + gas/doc/Makefile.in | 1 + gas/doc/as.texi | 7 - gas/doc/c-aarch64.texi | 2 - gas/dwarf2dbg.c | 33 +- gas/po/fr.po | 7239 ++++----- gas/po/uk.po | 7237 ++++----- gas/read.c | 3 + gas/testsuite/gas/aarch64/csre-invalid.d | 3 - gas/testsuite/gas/aarch64/csre-invalid.s | 6 - gas/testsuite/gas/aarch64/csre.d | 29 - gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 - gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 - gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 - gas/testsuite/gas/aarch64/csre_csr.d | 10 - gas/testsuite/gas/aarch64/csre_csr.s | 4 - gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/elf/dwarf2-20.d | 4 - gas/testsuite/gas/elf/elf.exp | 5 - gas/testsuite/gas/elf/warn-2.s | 7 - gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/m68hc11/indexed12.d | 4 - gas/testsuite/gas/ppc/power4.d | 1 - gas/testsuite/gas/ppc/test1elf32.d | 1 - gas/testsuite/gas/ppc/test1elf64.d | 1 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 540 + gdb/MAINTAINERS | 5 +- gdb/aarch64-linux-tdep.c | 16 +- gdb/aarch64-tdep.c | 148 +- gdb/ada-lang.c | 4 +- gdb/alpha-mdebug-tdep.c | 4 +- gdb/alpha-tdep.c | 8 +- gdb/amd64-fbsd-tdep.c | 2 +- gdb/amd64-linux-tdep.c | 4 +- gdb/amd64-obsd-tdep.c | 2 +- gdb/arc-linux-nat.c | 16 +- gdb/arc-linux-tdep.c | 47 +- gdb/arc-newlib-tdep.c | 11 +- gdb/arc-tdep.c | 155 +- gdb/arc-tdep.h | 7 +- gdb/arch/aarch64-insn.c | 9 +- gdb/arch/aarch64-insn.h | 5 + gdb/arm-linux-tdep.c | 2 +- gdb/arm-tdep.c | 50 +- gdb/auto-load.c | 214 +- gdb/auto-load.h | 25 +- gdb/avr-tdep.c | 6 +- gdb/cli/cli-cmds.c | 36 - gdb/coffread.c | 4 +- gdb/compile/compile-c-types.c | 12 +- gdb/compile/compile-cplus-types.c | 6 +- gdb/compile/compile.c | 4 +- gdb/copyright.py | 2 +- gdb/cris-tdep.c | 11 +- gdb/csky-tdep.c | 4 +- gdb/doc/ChangeLog | 32 + gdb/doc/gdb.texinfo | 410 +- gdb/doc/python.texi | 4 + gdb/dwarf2/loc.c | 6 +- gdb/dwarf2/read.c | 22 +- gdb/expprint.c | 9 +- gdb/extension-priv.h | 2 +- gdb/extension.c | 7 +- gdb/extension.h | 5 +- gdb/f-exp.y | 36 +- gdb/f-valprint.c | 5 - gdb/features/aarch64-fpu.c | 5 + gdb/features/aarch64-fpu.xml | 2 + gdb/frame.c | 20 +- gdb/frame.h | 16 +- gdb/frv-tdep.c | 2 +- gdb/gdb_bfd.c | 70 +- gdb/gdbarch.c | 2 +- gdb/gdbtypes.c | 82 +- gdb/gdbtypes.h | 61 +- gdb/gnu-v2-abi.c | 2 +- gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-auto-load.c | 5 +- gdb/guile/scm-type.c | 4 +- gdb/hppa-tdep.c | 26 +- gdb/i386-fbsd-tdep.c | 16 +- gdb/i386-gnu-tdep.c | 2 +- gdb/i386-linux-tdep.c | 10 +- gdb/i386-netbsd-tdep.c | 2 +- gdb/i386-obsd-tdep.c | 2 +- gdb/i386-tdep.c | 12 +- gdb/i387-tdep.c | 6 +- gdb/ia64-tdep.c | 6 +- gdb/infrun.c | 4 +- gdb/jit.c | 80 +- gdb/language.c | 4 +- gdb/linux-nat.c | 2 +- gdb/linux-thread-db.c | 11 +- gdb/lm32-tdep.c | 4 +- gdb/m32r-linux-tdep.c | 10 +- gdb/m32r-tdep.c | 4 +- gdb/m68hc11-tdep.c | 4 +- gdb/m68k-linux-tdep.c | 2 +- gdb/m68k-tdep.c | 6 +- gdb/main.c | 17 +- gdb/maint-test-options.c | 2 +- gdb/mep-tdep.c | 2 +- gdb/mi/mi-cmds.c | 5 +- gdb/mips-tdep.c | 40 +- gdb/nat/amd64-linux-siginfo.c | 13 + gdb/nat/linux-osdata.c | 2 +- gdb/objfiles.h | 3 +- gdb/parse.c | 7 +- gdb/ppc-fbsd-tdep.c | 4 +- gdb/ppc-netbsd-tdep.c | 2 +- gdb/ppc-obsd-tdep.c | 4 +- gdb/progspace.c | 2 +- gdb/python/py-auto-load.c | 5 +- gdb/python/py-breakpoint.c | 8 +- gdb/python/py-param.c | 7 +- gdb/python/py-record-btrace.c | 2 +- gdb/python/py-record.c | 2 +- gdb/python/py-type.c | 10 +- gdb/python/python-internal.h | 5 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/record.c | 2 +- gdb/regcache.c | 2 +- gdb/registry.h | 2 +- gdb/remote-sim.c | 1 + gdb/remote.c | 661 +- gdb/remote.h | 20 + gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-tdep.c | 59 +- gdb/riscv-tdep.h | 23 + gdb/rs6000-tdep.c | 18 +- gdb/rust-lang.c | 2 +- gdb/s390-tdep.c | 14 +- gdb/score-tdep.c | 18 +- gdb/ser-tcp.c | 2 +- gdb/serial.c | 7 +- gdb/serial.h | 8 + gdb/solib-aix.c | 23 +- gdb/sparc-netbsd-tdep.c | 2 +- gdb/sparc-sol2-tdep.c | 2 +- gdb/sparc64-netbsd-tdep.c | 2 +- gdb/sparc64-sol2-tdep.c | 2 +- gdb/stap-probe.c | 31 +- gdb/symfile.c | 10 +- gdb/symfile.h | 8 + gdb/symmisc.c | 6 +- gdb/target.h | 9 - gdb/testsuite/ChangeLog | 117 + gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 + gdb/testsuite/gdb.arch/amd64-stap-expressions.S | 43 + gdb/testsuite/gdb.arch/amd64-stap-expressions.exp | 68 + gdb/testsuite/gdb.arch/amd64-stap-three-arg-disp.S | 5 +- gdb/testsuite/gdb.arch/i386-mpx-call.c | 78 +- gdb/testsuite/gdb.arch/i386-mpx-call.exp | 17 +- gdb/testsuite/gdb.arch/i386-mpx-map.c | 45 +- gdb/testsuite/gdb.arch/i386-mpx-map.exp | 23 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.c | 80 +- gdb/testsuite/gdb.arch/i386-mpx-sigsegv.exp | 15 +- gdb/testsuite/gdb.arch/i386-mpx-simple_segv.c | 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rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => 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}/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename sim/testsuite/{sim => }/bfin/cc0.s (100%) rename sim/testsuite/{sim => }/bfin/cc1.s (100%) rename sim/testsuite/{sim => }/bfin/cc5.S (100%) rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%) rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%) rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%) rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%) rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%) rename 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=> }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs (100%) rename sim/testsuite/{sim => }/frv/cop2.cgs (100%) rename sim/testsuite/{sim => }/frv/cor.cgs (100%) rename sim/testsuite/{sim => }/frv/corcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) create mode 100644 sim/testsuite/frv/exit47.ms rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) 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rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldq.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%) rename sim/testsuite/{sim => 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}/frv/notcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%) rename sim/testsuite/{sim => }/frv/or.cgs (100%) rename sim/testsuite/{sim => }/frv/orcc.cgs (100%) rename sim/testsuite/{sim => }/frv/orcr.cgs (100%) rename sim/testsuite/{sim => }/frv/ori.cgs (100%) rename sim/testsuite/{sim => }/frv/oricc.cgs (100%) rename sim/testsuite/{sim => }/frv/orncr.cgs (100%) rename sim/testsuite/{sim => }/frv/parallel.exp (100%) rename sim/testsuite/{sim => }/frv/ret.cgs (100%) rename sim/testsuite/{sim => }/frv/rett.cgs (100%) rename sim/testsuite/{sim => }/frv/scan.cgs (100%) rename sim/testsuite/{sim => }/frv/scani.cgs (100%) rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethi.cgs (100%) rename sim/testsuite/{sim => }/frv/sethilo.pcgs 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