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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-allyesconfig in repository toolchain/ci/llvm-project.
from e8a397203c67 llvm-dwarfdump: Fix DWARF-5 DW_FORM_implicit_const (used by GCC) adds b6ff4dd2e99e [PowerPC] Handle FP physical register in inline asm constraint. adds 07234c7d6bc2 Add type attributes to LLVM C API adds fd2737946391 [ARM] MVE VPT block tests with debug info. NFC adds c7381b628d63 [ARM] Skip debug during vpt block creation adds a3543fd9d470 [ARM] Handle debug instrs in ARM Low Overhead Loop pass adds 0f3fec4618e4 [ARM] Guard against loop variant gather ptr operands adds e2e2057132c1 [ARM] Ensure loop invariant active.lane.mask operands adds 1a8f0b969c4e [ARM] Clean up some tests, removing dead instructions. NFC adds f83afe6ae961 [ARM] Ensure instructions are simplified prior to GatherSc [...] adds d29ae443aa40 [ARM] Fix Changed status in MVEGatherScatterLoweringPass. adds b7c7b42db1d1 [ARM] Use just ARM::t2B in ARMBlockPlacementPass adds fed41342a82f Revert "Revert "[Coverage] Fix branch coverage merging in [...]
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Summary of changes: llvm/include/llvm-c/Core.h | 12 + llvm/lib/IR/Core.cpp | 16 + llvm/lib/Target/ARM/ARMBlockPlacement.cpp | 7 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 20 +- llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp | 5 +- llvm/lib/Target/ARM/MVETailPredication.cpp | 4 + llvm/lib/Target/ARM/MVEVPTBlockPass.cpp | 13 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 41 ++- .../CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll | 23 ++ .../CodeGen/PowerPC/inline-asm-physical-fpr.ll | 26 ++ .../cond-vector-reduce-mve-codegen.ll | 82 +---- .../Thumb2/LowOverheadLoops/extending-loads.ll | 44 --- .../Thumb2/LowOverheadLoops/fast-fp-loops.ll | 22 -- .../Thumb2/LowOverheadLoops/mve-tail-data-types.ll | 121 -------- .../test/CodeGen/Thumb2/LowOverheadLoops/nested.ll | 30 -- .../CodeGen/Thumb2/LowOverheadLoops/reductions.ll | 10 - .../CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll | 2 +- .../Thumb2/LowOverheadLoops/skip-vpt-debug.mir | 330 +++++++++++++++++++++ .../Thumb2/LowOverheadLoops/tail-pred-basic.ll | 45 --- .../Thumb2/LowOverheadLoops/tail-pred-const.ll | 40 --- .../tail-pred-disabled-in-loloops.ll | 4 - .../tail-pred-intrinsic-add-sat.ll | 2 - .../LowOverheadLoops/tail-pred-intrinsic-fabs.ll | 1 - .../LowOverheadLoops/tail-pred-intrinsic-round.ll | 6 - .../tail-pred-intrinsic-sub-sat.ll | 2 - .../Thumb2/LowOverheadLoops/tail-pred-reduce.ll | 25 -- .../Thumb2/LowOverheadLoops/tail-pred-widen.ll | 28 +- .../LowOverheadLoops/varying-outer-2d-reduction.ll | 1 - .../LowOverheadLoops/vector-arith-codegen.ll | 89 +----- .../LowOverheadLoops/vector-reduce-mve-tail.ll | 9 - llvm/test/CodeGen/Thumb2/block-placement.mir | 4 +- llvm/test/CodeGen/Thumb2/lsll0.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-fma-loops.ll | 156 +--------- llvm/test/CodeGen/Thumb2/mve-gather-increment.ll | 2 - .../CodeGen/Thumb2/mve-gather-optimisation-deep.ll | 73 +++-- .../Thumb2/mve-gather-scatter-optimisation.ll | 85 +++--- llvm/test/CodeGen/Thumb2/mve-gather-unused.ll | 38 +++ llvm/test/CodeGen/Thumb2/mve-phireg.ll | 2 +- llvm/test/CodeGen/Thumb2/mve-pred-xor.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-selectcc.ll | 2 +- .../CodeGen/Thumb2/mve-tailpred-loopinvariant.ll | 145 +++++++++ llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll | 15 - llvm/test/CodeGen/Thumb2/mve-vpt-block-debug.mir | 110 +++++++ llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll | 22 +- llvm/test/tools/llvm-cov/branch-templates.cpp | 16 +- llvm/tools/llvm-cov/CoverageSummaryInfo.cpp | 6 +- llvm/tools/llvm-cov/CoverageSummaryInfo.h | 5 + 47 files changed, 928 insertions(+), 819 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr.ll create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-gather-unused.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vpt-block-debug.mir