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from 3d7e4a4b98b [X86] Make better use of instregex for cmovcc/setcc/jcc ins [...] new 10c6c76ce2d Move tests to the correct place new 9334f5c86b8 Split TailDuplicatePass into pre- and post-RA variant; NFC
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Summary of changes: include/llvm/CodeGen/Passes.h | 4 ++ include/llvm/CodeGen/TargetPassConfig.h | 4 -- include/llvm/InitializePasses.h | 3 +- lib/CodeGen/CodeGen.cpp | 3 +- lib/CodeGen/TailDuplication.cpp | 59 +++++++++++++--------- lib/CodeGen/TargetPassConfig.cpp | 4 +- test/CodeGen/{MIR => }/AArch64/spill-fold.mir | 0 test/CodeGen/{MIR => }/AMDGPU/fold-imm-f16-f32.mir | 0 test/CodeGen/{MIR => }/AMDGPU/fold-multiple.mir | 0 .../AMDGPU/memory-legalizer-atomic-insert-end.mir | 0 ...ory-legalizer-multiple-mem-operands-atomics.mir | 0 ...galizer-multiple-mem-operands-nontemporal-1.mir | 0 ...galizer-multiple-mem-operands-nontemporal-2.mir | 0 .../ARM/PR32721_ifcvt_triangle_unanalyzable.mir | 0 .../{MIR => }/ARM/ifcvt_canFallThroughTo.mir | 0 .../{MIR => }/ARM/ifcvt_diamond_unanalyzable.mir | 0 .../ARM/ifcvt_forked_diamond_unanalyzable.mir | 0 .../ARM/ifcvt_simple_bad_zero_prob_succ.mir | 0 .../{MIR => }/ARM/ifcvt_simple_unanalyzable.mir | 0 .../ARM/ifcvt_triangleWoCvtToNextEdge.mir | 0 test/CodeGen/{MIR => }/X86/dynamic-regmask.ll | 0 test/CodeGen/{MIR => }/X86/opt_phis.mir | 0 .../{MIR => }/X86/shrink_wrap_dbg_value.mir | 0 .../X86/simple-register-allocation-read-undef.mir | 0 test/CodeGen/X86/tail-dup-debugloc.ll | 2 +- .../{MIR => }/X86/unreachable-mbb-undef-phi.mir | 0 26 files changed, 46 insertions(+), 33 deletions(-) rename test/CodeGen/{MIR => }/AArch64/spill-fold.mir (100%) rename test/CodeGen/{MIR => }/AMDGPU/fold-imm-f16-f32.mir (100%) rename test/CodeGen/{MIR => }/AMDGPU/fold-multiple.mir (100%) rename test/CodeGen/{MIR => }/AMDGPU/memory-legalizer-atomic-insert-end.mir (100%) rename test/CodeGen/{MIR => }/AMDGPU/memory-legalizer-multiple-mem-operands-atomic [...] rename test/CodeGen/{MIR => }/AMDGPU/memory-legalizer-multiple-mem-operands-nontem [...] rename test/CodeGen/{MIR => }/AMDGPU/memory-legalizer-multiple-mem-operands-nontem [...] rename test/CodeGen/{MIR => }/ARM/PR32721_ifcvt_triangle_unanalyzable.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_canFallThroughTo.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_diamond_unanalyzable.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_forked_diamond_unanalyzable.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_simple_bad_zero_prob_succ.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_simple_unanalyzable.mir (100%) rename test/CodeGen/{MIR => }/ARM/ifcvt_triangleWoCvtToNextEdge.mir (100%) rename test/CodeGen/{MIR => }/X86/dynamic-regmask.ll (100%) rename test/CodeGen/{MIR => }/X86/opt_phis.mir (100%) rename test/CodeGen/{MIR => }/X86/shrink_wrap_dbg_value.mir (100%) rename test/CodeGen/{MIR => }/X86/simple-register-allocation-read-undef.mir (100%) rename test/CodeGen/{MIR => }/X86/unreachable-mbb-undef-phi.mir (100%)