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from 01b1ccb97d4 [AArch64InstrInfo] Stop getInstSizeInBytes returning non-ze [...] new 9cb033fcdc6 [X86][SSE] Add shuffled load tests from PR16739 new 88b99765a8d [RISCV] Convert registers from unsigned to Register
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Summary of changes: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 65 +++---- .../RISCV/Disassembler/RISCVDisassembler.cpp | 19 +- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 3 +- .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 3 +- lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 10 +- lib/Target/RISCV/RISCVFrameLowering.cpp | 24 +-- lib/Target/RISCV/RISCVFrameLowering.h | 2 +- lib/Target/RISCV/RISCVISelLowering.cpp | 24 +-- lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- lib/Target/RISCV/RISCVInstrInfo.h | 2 +- lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 6 +- test/CodeGen/X86/load-partial.ll | 212 +++++++++++++++++++++ 12 files changed, 294 insertions(+), 78 deletions(-)