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from 9fa92ef02a4 [MCA] Improved cost computation for loop carried dependenci [...] new db7d9c2217a Reapply r372285 "GlobalISel: Don't materialize immarg argum [...] new 09626b4e35d [Float2Int] avoid crashing on unreachable code (PR38502)
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Summary of changes: .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 5 + .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 14 +- include/llvm/CodeGen/ScheduleDAGInstrs.h | 3 + include/llvm/Target/TargetSelectionDAG.td | 5 + include/llvm/Transforms/Scalar/Float2Int.h | 6 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 27 +- lib/CodeGen/ScheduleDAGInstrs.cpp | 10 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 18 +- lib/Target/AArch64/AArch64InstrFormats.td | 4 +- lib/Target/AArch64/AArch64InstrInfo.td | 2 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 279 +++++++- lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 7 + lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 60 ++ lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 5 + lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 399 ++++++++++- lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 40 +- lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 +- lib/Target/AMDGPU/AMDGPUSubtarget.h | 4 + lib/Target/AMDGPU/BUFInstructions.td | 110 +-- lib/Target/AMDGPU/DSInstructions.td | 2 +- lib/Target/AMDGPU/SIISelLowering.cpp | 104 +-- lib/Target/AMDGPU/SIInstructions.td | 12 +- lib/Target/AMDGPU/SOPInstructions.td | 14 +- lib/Target/AMDGPU/VOP1Instructions.td | 18 +- lib/Target/AMDGPU/VOP3Instructions.td | 44 +- lib/Target/ARM/ARMISelLowering.cpp | 24 +- lib/Target/ARM/ARMInstrInfo.td | 52 +- lib/Target/ARM/ARMInstrThumb2.td | 48 +- lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 696 +++++++++--------- lib/Target/Hexagon/HexagonDepOperands.td | 83 ++- lib/Target/Hexagon/HexagonIntrinsics.td | 46 +- lib/Target/Mips/MicroMipsDSPInstrInfo.td | 4 +- lib/Target/Mips/Mips64InstrInfo.td | 1 + lib/Target/Mips/MipsDSPInstrInfo.td | 19 +- lib/Target/Mips/MipsInstrInfo.td | 2 + lib/Target/Mips/MipsMSAInstrInfo.td | 55 +- lib/Target/Mips/MipsSEISelLowering.cpp | 3 +- lib/Target/PowerPC/PPCInstrAltivec.td | 6 +- lib/Target/PowerPC/PPCInstrVSX.td | 4 +- lib/Target/RISCV/RISCVInstrInfoA.td | 8 +- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 6 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 49 +- lib/Target/SystemZ/SystemZInstrFormats.td | 166 ++--- lib/Target/SystemZ/SystemZInstrVector.td | 18 +- lib/Target/SystemZ/SystemZOperands.td | 121 ++-- lib/Target/SystemZ/SystemZOperators.td | 6 +- lib/Target/SystemZ/SystemZPatterns.td | 4 +- lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp | 8 +- .../WebAssembly/WebAssemblyInstrBulkMemory.td | 4 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 12 +- lib/Target/X86/X86ISelLowering.cpp | 270 ++++--- lib/Target/X86/X86InstrAVX512.td | 224 +++--- lib/Target/X86/X86InstrMMX.td | 8 +- lib/Target/X86/X86InstrSSE.td | 204 +++--- lib/Target/X86/X86InstrSystem.td | 2 +- lib/Target/X86/X86InstrTSX.td | 2 +- lib/Target/X86/X86InstrXOP.td | 16 +- lib/Transforms/Scalar/Float2Int.cpp | 47 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 3 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir | 12 +- .../GlobalISel/inst-select-amdgcn.s.sendmsg.mir | 3 +- .../GlobalISel/irtranslator-amdgcn-sendmsg.ll | 15 + .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll | 12 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 9 +- .../irtranslator-struct-return-intrinsics.ll | 5 +- .../llvm.amdgcn.raw.buffer.store.format.f16.ll | 519 ++++++++++++++ .../llvm.amdgcn.raw.buffer.store.format.f32.ll | 314 ++++++++ .../GlobalISel/llvm.amdgcn.raw.buffer.store.ll | 791 +++++++++++++++++++++ .../AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll | 45 ++ .../AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.ds.swizzle.mir | 21 + .../regbankselect-amdgcn.image.load.1d.ll | 181 +++++ .../regbankselect-amdgcn.image.sample.1d.ll | 268 +++++++ .../regbankselect-amdgcn.raw.buffer.load.ll | 173 +++++ .../regbankselect-amdgcn.struct.buffer.load.ll | 179 +++++ .../regbankselect-amdgcn.struct.buffer.store.ll | 174 +++++ .../AMDGPU/GlobalISel/regbankselect-smulh.mir | 62 +- .../AMDGPU/GlobalISel/regbankselect-umulh.mir | 62 +- ...hed-assert-dead-def-subreg-use-other-subreg.mir | 70 ++ test/Other/opt-O2-pipeline.ll | 2 +- test/Other/opt-O3-pipeline.ll | 2 +- test/Other/opt-Os-pipeline.ll | 2 +- test/TableGen/immarg.td | 31 + test/Transforms/Float2Int/basic.ll | 22 + utils/TableGen/GlobalISelEmitter.cpp | 27 +- 85 files changed, 5068 insertions(+), 1388 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.for [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.for [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buff [...] create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buff [...] create mode 100644 test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir create mode 100644 test/TableGen/immarg.td