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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/gcc.
from 8d36a0d2880 Daily bump. adds 402d28998fa RISC-V: Fix wrong zifencei handling in riscv_subset_list::t [...] adds e166cada081 Extend vpcmov to handle V8HF/V16HFmode under TARGET_XOP. adds 4f442a3bcb9 x86: Update -mtune=alderlake adds a97fdde627e rs6000/doc: Rename future cpu with power10
No new revisions were added by this update.
Summary of changes: gcc/common/config/riscv/riscv-common.c | 2 +- gcc/config/i386/i386-options.c | 4 +- gcc/config/i386/i386.c | 1 + gcc/config/i386/sse.md | 8 +-- gcc/config/i386/x86-tune-costs.h | 120 +++++++++++++++++++++++++++++++ gcc/config/i386/x86-tune-sched.c | 2 + gcc/config/i386/x86-tune.def | 58 +++++++-------- gcc/doc/invoke.texi | 24 +++---- gcc/testsuite/gcc.target/i386/pr103151.c | 18 +++++ 9 files changed, 190 insertions(+), 47 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr103151.c