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from 880834d3e7e Daily bump. new e96d4bf6a6e RISC-V: Refactor gen zero_extend rtx for SAT_* when expand [...] new 72f3e9021e5 RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM new 56ed1dfa79c RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM new ea81e21d539 RISC-V: Add testcases for unsigned scalar quad and oct .SAT [...] new 5239902210a RISC-V: Add testcases for unsigned scalar quad and oct .SAT [...]
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Summary of changes: gcc/config/riscv/riscv.cc | 99 ++++++++++------------ ...ec_sat_u_add_imm-2.c => vec_sat_u_add_imm-10.c} | 4 +- ...ec_sat_u_add_imm-7.c => vec_sat_u_add_imm-11.c} | 4 +- ...ec_sat_u_add_imm-7.c => vec_sat_u_add_imm-12.c} | 4 +- ...ec_sat_u_add_imm-1.c => vec_sat_u_add_imm-13.c} | 4 +- ...ec_sat_u_add_imm-2.c => vec_sat_u_add_imm-14.c} | 4 +- ...ec_sat_u_add_imm-7.c => vec_sat_u_add_imm-15.c} | 4 +- ...ec_sat_u_add_imm-7.c => vec_sat_u_add_imm-16.c} | 4 +- ...vec_sat_u_add_imm-1.c => vec_sat_u_add_imm-9.c} | 4 +- .../rvv/autovec/binop/vec_sat_u_add_imm-run-10.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-11.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-12.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-13.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-14.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-15.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-16.c | 28 ++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-run-9.c | 28 ++++++ .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 20 +++++ gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-3.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-43.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub-7.c | 4 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c | 2 + .../gcc.target/riscv/sat_u_sub_imm-11_1.c | 2 + .../gcc.target/riscv/sat_u_sub_imm-11_2.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-15.c | 2 + .../gcc.target/riscv/sat_u_sub_imm-15_1.c | 2 + .../gcc.target/riscv/sat_u_sub_imm-15_2.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_1.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-3_2.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c | 2 + gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c | 2 + .../riscv/{sat_u_trunc-1.c => sat_u_trunc-10.c} | 4 +- .../riscv/{sat_u_trunc-1.c => sat_u_trunc-11.c} | 4 +- .../riscv/{sat_u_trunc-2.c => sat_u_trunc-12.c} | 4 +- .../riscv/{sat_u_trunc-1.c => sat_u_trunc-16.c} | 4 +- .../riscv/{sat_u_trunc-1.c => sat_u_trunc-17.c} | 4 +- .../riscv/{sat_u_trunc-2.c => sat_u_trunc-18.c} | 4 +- .../{sat_u_trunc-run-8.c => sat_u_trunc-run-10.c} | 2 +- .../{sat_u_trunc-run-9.c => sat_u_trunc-run-11.c} | 2 +- .../{sat_u_trunc-run-9.c => sat_u_trunc-run-12.c} | 2 +- .../{sat_u_trunc-run-14.c => sat_u_trunc-run-16.c} | 2 +- .../{sat_u_trunc-run-13.c => sat_u_trunc-run-17.c} | 2 +- .../{sat_u_trunc-run-14.c => sat_u_trunc-run-18.c} | 2 +- 54 files changed, 396 insertions(+), 87 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-2.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-7.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-7.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-1.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-2.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-7.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-7.c => ve [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add_imm-1.c => ve [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_ [...] copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-1.c => sat_u_trunc-10.c} (85%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-1.c => sat_u_trunc-11.c} (85%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-2.c => sat_u_trunc-12.c} (86%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-1.c => sat_u_trunc-16.c} (85%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-1.c => sat_u_trunc-17.c} (85%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-2.c => sat_u_trunc-18.c} (86%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-8.c => sat_u_trunc-run-10.c} (95%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-9.c => sat_u_trunc-run-11.c} (95%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-9.c => sat_u_trunc-run-12.c} (95%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-14.c => sat_u_trunc-run-16.c} (95%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-13.c => sat_u_trunc-run-17.c} (95%) copy gcc/testsuite/gcc.target/riscv/{sat_u_trunc-run-14.c => sat_u_trunc-run-18.c} (95%)
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