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from 326d4745a28 Daily bump. new aedb306a457 RISC-V: Fix RVV strided load/store testcases failure new 12e30d82cc7 RISC-V: Fix incorrect optimization options passing to widden

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Summary of changes: .../rvv/autovec/strided/strided_ld_st-1-f16.c | 32 +++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-f32.c | 32 +++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-f64.c | 2 +- .../rvv/autovec/strided/strided_ld_st-1-i16.c | 32 +++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-i32.c | 46 ++++++++++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-i64.c | 2 +- .../riscv/rvv/autovec/strided/strided_ld_st-1-i8.c | 32 +++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-u16.c | 32 +++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-u32.c | 46 ++++++++++++++++++---- .../rvv/autovec/strided/strided_ld_st-1-u64.c | 2 +- .../riscv/rvv/autovec/strided/strided_ld_st-1-u8.c | 32 +++++++++++---- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +- 12 files changed, 232 insertions(+), 60 deletions(-)