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from b404df708c2 [MIPS GlobalISel] Combine extending loads new 8993a7805dc [MIPS GlobalISel] Select zero extending and sign extending load
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Summary of changes: lib/Target/Mips/MipsInstructionSelector.cpp | 32 ++++++- lib/Target/Mips/MipsLegalizerInfo.cpp | 5 ++ lib/Target/Mips/MipsRegisterBankInfo.cpp | 2 + .../instruction-select/zextLoad_and_sextLoad.mir | 98 ++++++++++++++++++++++ .../zextLoad_and_sextLoad.mir | 40 ++++----- .../GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll | 98 ++++++++++++++++++++++ .../regbankselect/zextLoad_and_sextLoad.mir | 94 +++++++++++++++++++++ 7 files changed, 342 insertions(+), 27 deletions(-) create mode 100644 test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_se [...] copy test/CodeGen/Mips/GlobalISel/{mips-prelegalizer-combiner => legalizer}/zextLo [...] create mode 100644 test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll create mode 100644 test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir