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from c77085970ec [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor [...] new 65f27c18e34 [RISC-V] Clear both upper and lower bits using 3 shifts

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Summary of changes: gcc/config/riscv/riscv.cc | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)