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unknown user pushed a change to branch master in repository llvm.

from 26392263c3d [Attributor] Use the cached data layout directly new b0ee1d2cfb5 [AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC. new 1311d23a622 [webassembly] Apply llvm-prefer-register-over-unsigned from [...] new a065117c6a7 [aarch64] Apply llvm-prefer-register-over-unsigned from cla [...] new cf1063f8cbf [risc-v] Apply llvm-prefer-register-over-unsigned from clan [...]

The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp | 8 +-- lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp | 12 ++-- lib/Target/AArch64/AArch64AsmPrinter.cpp | 76 +++++++++++----------- lib/Target/AArch64/AArch64CondBrTuning.cpp | 2 +- lib/Target/AArch64/AArch64ConditionalCompares.cpp | 4 +- .../AArch64/AArch64DeadRegisterDefinitionsPass.cpp | 2 +- lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 30 ++++----- lib/Target/AArch64/AArch64FalkorHWPFFix.cpp | 2 +- lib/Target/AArch64/AArch64FastISel.cpp | 18 ++--- lib/Target/AArch64/AArch64FrameLowering.cpp | 10 +-- lib/Target/AArch64/AArch64ISelLowering.cpp | 12 ++-- lib/Target/AArch64/AArch64InstrInfo.cpp | 52 +++++++-------- lib/Target/AArch64/AArch64InstructionSelector.cpp | 20 +++--- lib/Target/AArch64/AArch64LegalizerInfo.cpp | 2 +- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 34 +++++----- lib/Target/AArch64/AArch64PBQPRegAlloc.cpp | 6 +- lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 10 +-- lib/Target/AArch64/AArch64RegisterInfo.cpp | 2 +- lib/Target/AArch64/AArch64SIMDInstrOpt.cpp | 8 +-- lib/Target/AArch64/AArch64SpeculationHardening.cpp | 6 +- lib/Target/AArch64/AArch64StorePairSuppress.cpp | 2 +- lib/Target/AMDGPU/MIMGInstructions.td | 4 +- lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 44 ++++++------- lib/Target/RISCV/RISCVFrameLowering.cpp | 4 +- lib/Target/RISCV/RISCVISelLowering.cpp | 36 +++++----- lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 10 +-- lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 2 +- lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp | 2 +- .../WebAssembly/WebAssemblyExplicitLocals.cpp | 16 ++--- .../WebAssemblyFixIrreducibleControlFlow.cpp | 2 +- .../WebAssembly/WebAssemblyFrameLowering.cpp | 8 +-- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 12 ++-- .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 6 +- .../WebAssembly/WebAssemblyLowerBrUnless.cpp | 4 +- .../WebAssembly/WebAssemblyMemIntrinsicResults.cpp | 4 +- lib/Target/WebAssembly/WebAssemblyPeephole.cpp | 10 +-- lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | 18 ++--- lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp | 4 +- lib/Target/WebAssembly/WebAssemblyUtilities.cpp | 2 +- 41 files changed, 255 insertions(+), 255 deletions(-)