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from f3d0c95570d AArch64: Extend intrinsics framework to account for merging [...] new 9b1141fa8fc [RISC-V][PR target/120674] Avoid division by zero in dwarf [...]

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Summary of changes: gcc/config/riscv/riscv.cc | 7 +++++++ gcc/testsuite/gcc.target/riscv/pr120674.c | 6 ++++++ 2 files changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr120674.c