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from daa39fa1446 [TTI, AArch64] Add transpose shuffle kind new 0faf8b4d623 [RISCV] Add test case showing suboptimal codegen when loadi [...] new cdb6162eae2 [RISCV] Implement isZextFree

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Summary of changes: lib/Target/RISCV/RISCVISelLowering.cpp | 14 +++++ lib/Target/RISCV/RISCVISelLowering.h | 1 + test/CodeGen/RISCV/zext-with-load-is-free.ll | 76 ++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 test/CodeGen/RISCV/zext-with-load-is-free.ll