This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from b899068e607 [Hexagon] Fix instruction selection for vselect v4i8 new 57a81294076 Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/CodeGen/AggressiveAntiDepBreaker.cpp | 14 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 6 +- lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 4 +- lib/CodeGen/BranchFolding.cpp | 12 +- lib/CodeGen/BreakFalseDeps.cpp | 4 +- lib/CodeGen/CalcSpillWeights.cpp | 2 +- lib/CodeGen/CriticalAntiDepBreaker.cpp | 8 +- lib/CodeGen/DeadMachineInstructionElim.cpp | 6 +- lib/CodeGen/DetectDeadLanes.cpp | 18 +- lib/CodeGen/EarlyIfConversion.cpp | 8 +- lib/CodeGen/ExpandPostRAPseudos.cpp | 6 +- lib/CodeGen/GlobalISel/CSEInfo.cpp | 2 +- lib/CodeGen/GlobalISel/CombinerHelper.cpp | 14 +- lib/CodeGen/GlobalISel/InstructionSelect.cpp | 4 +- lib/CodeGen/GlobalISel/Localizer.cpp | 8 +- lib/CodeGen/GlobalISel/Utils.cpp | 10 +- lib/CodeGen/IfConversion.cpp | 4 +- lib/CodeGen/ImplicitNullChecks.cpp | 8 +- lib/CodeGen/InlineSpiller.cpp | 4 +- lib/CodeGen/LiveDebugValues.cpp | 6 +- lib/CodeGen/LiveDebugVariables.cpp | 8 +- lib/CodeGen/LiveIntervals.cpp | 4 +- lib/CodeGen/LivePhysRegs.cpp | 10 +- lib/CodeGen/LiveRangeEdit.cpp | 6 +- lib/CodeGen/LiveRangeShrink.cpp | 2 +- lib/CodeGen/LiveRegMatrix.cpp | 2 +- lib/CodeGen/LiveRegUnits.cpp | 6 +- lib/CodeGen/LiveVariables.cpp | 6 +- lib/CodeGen/MIRCanonicalizerPass.cpp | 8 +- lib/CodeGen/MachineBasicBlock.cpp | 10 +- lib/CodeGen/MachineCSE.cpp | 18 +- lib/CodeGen/MachineCopyPropagation.cpp | 34 +-- lib/CodeGen/MachineInstrBundle.cpp | 6 +- lib/CodeGen/MachineLICM.cpp | 34 +-- lib/CodeGen/MachineOperand.cpp | 2 +- lib/CodeGen/MachinePipeliner.cpp | 38 ++-- lib/CodeGen/MachineSSAUpdater.cpp | 4 +- lib/CodeGen/MachineScheduler.cpp | 6 +- lib/CodeGen/MachineSink.cpp | 18 +- lib/CodeGen/MachineTraceMetrics.cpp | 10 +- lib/CodeGen/MachineVerifier.cpp | 4 +- lib/CodeGen/OptimizePHIs.cpp | 8 +- lib/CodeGen/PHIElimination.cpp | 8 +- lib/CodeGen/PeepholeOptimizer.cpp | 26 +-- lib/CodeGen/ProcessImplicitDefs.cpp | 4 +- lib/CodeGen/RegAllocFast.cpp | 30 +-- lib/CodeGen/RegAllocGreedy.cpp | 4 +- lib/CodeGen/RegisterCoalescer.cpp | 12 +- lib/CodeGen/RegisterPressure.cpp | 4 +- lib/CodeGen/RegisterScavenging.cpp | 8 +- lib/CodeGen/RenameIndependentSubregs.cpp | 2 +- lib/CodeGen/ScheduleDAGInstrs.cpp | 18 +- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 12 +- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 2 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 7 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- lib/CodeGen/ShrinkWrap.cpp | 2 +- lib/CodeGen/SplitKit.cpp | 4 +- lib/CodeGen/StackMaps.cpp | 4 +- lib/CodeGen/TailDuplicator.cpp | 20 +- lib/CodeGen/TargetInstrInfo.cpp | 20 +- lib/CodeGen/TargetSchedule.cpp | 2 +- lib/CodeGen/TwoAddressInstructionPass.cpp | 42 ++-- lib/CodeGen/UnreachableBlockElim.cpp | 4 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 40 ++-- lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 26 +-- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 +- lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 8 +- lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 20 +- lib/Target/AMDGPU/GCNNSAReassign.cpp | 6 +- lib/Target/AMDGPU/GCNRegBankReassign.cpp | 6 +- lib/Target/AMDGPU/GCNRegPressure.cpp | 2 +- lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp | 4 +- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 22 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- lib/Target/AMDGPU/R600InstrInfo.cpp | 12 +- lib/Target/AMDGPU/R600MachineScheduler.cpp | 4 +- lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 10 +- lib/Target/AMDGPU/R600Packetizer.cpp | 4 +- lib/Target/AMDGPU/SIAddIMGInit.cpp | 4 +- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 24 +-- lib/Target/AMDGPU/SIFoldOperands.cpp | 12 +- lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 6 +- lib/Target/AMDGPU/SIFrameLowering.cpp | 28 +-- lib/Target/AMDGPU/SIISelLowering.cpp | 62 +++--- lib/Target/AMDGPU/SIInstrInfo.cpp | 234 ++++++++++----------- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 28 +-- lib/Target/AMDGPU/SILowerControlFlow.cpp | 6 +- lib/Target/AMDGPU/SILowerI1Copies.cpp | 12 +- lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 4 +- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 2 +- lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 8 +- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 2 +- lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 8 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 35 +-- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 12 +- lib/Target/AMDGPU/SIWholeQuadMode.cpp | 12 +- lib/Target/ARC/ARCISelLowering.cpp | 2 +- lib/Target/ARC/ARCOptAddrMode.cpp | 10 +- lib/Target/ARC/ARCRegisterInfo.cpp | 2 +- lib/Target/ARM/A15SDOptimizer.cpp | 32 +-- lib/Target/ARM/ARMAsmPrinter.cpp | 50 ++--- lib/Target/ARM/ARMBaseInstrInfo.cpp | 84 ++++---- lib/Target/ARM/ARMCallLowering.cpp | 2 +- lib/Target/ARM/ARMConstantIslandPass.cpp | 14 +- lib/Target/ARM/ARMExpandPseudoInsts.cpp | 58 ++--- lib/Target/ARM/ARMFastISel.cpp | 16 +- lib/Target/ARM/ARMFrameLowering.cpp | 6 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 +- lib/Target/ARM/ARMISelLowering.cpp | 114 +++++----- lib/Target/ARM/ARMInstrInfo.cpp | 2 +- lib/Target/ARM/ARMInstructionSelector.cpp | 30 +-- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 32 +-- lib/Target/ARM/MLxExpansionPass.cpp | 22 +- lib/Target/ARM/Thumb1FrameLowering.cpp | 8 +- lib/Target/ARM/Thumb2ITBlockPass.cpp | 6 +- lib/Target/ARM/Thumb2InstrInfo.cpp | 2 +- lib/Target/ARM/Thumb2SizeReduction.cpp | 28 +-- lib/Target/ARM/ThumbRegisterInfo.cpp | 4 +- lib/Target/AVR/AVRAsmPrinter.cpp | 2 +- lib/Target/AVR/AVRExpandPseudoInsts.cpp | 10 +- lib/Target/AVR/AVRFrameLowering.cpp | 2 +- lib/Target/AVR/AVRISelLowering.cpp | 12 +- lib/Target/AVR/AVRRegisterInfo.cpp | 2 +- lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- lib/Target/BPF/BPFISelLowering.cpp | 15 +- lib/Target/BPF/BPFInstrInfo.cpp | 6 +- lib/Target/BPF/BPFMIPeephole.cpp | 14 +- lib/Target/BPF/BPFMISimplifyPatchable.cpp | 4 +- lib/Target/BPF/BPFRegisterInfo.cpp | 6 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 2 +- lib/Target/Hexagon/HexagonBitSimplify.cpp | 38 ++-- lib/Target/Hexagon/HexagonBitTracker.cpp | 2 +- lib/Target/Hexagon/HexagonConstExtenders.cpp | 2 +- lib/Target/Hexagon/HexagonConstPropagation.cpp | 10 +- lib/Target/Hexagon/HexagonCopyToCombine.cpp | 30 +-- lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 18 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 8 +- lib/Target/Hexagon/HexagonFrameLowering.cpp | 50 ++--- lib/Target/Hexagon/HexagonGenInsert.cpp | 10 +- lib/Target/Hexagon/HexagonGenMux.cpp | 6 +- lib/Target/Hexagon/HexagonGenPredicate.cpp | 4 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 52 ++--- lib/Target/Hexagon/HexagonISelLowering.cpp | 4 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 104 ++++----- lib/Target/Hexagon/HexagonNewValueJump.cpp | 6 +- lib/Target/Hexagon/HexagonOptAddrMode.cpp | 10 +- lib/Target/Hexagon/HexagonPeephole.cpp | 24 +-- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 6 +- .../Hexagon/HexagonSplitConst32AndConst64.cpp | 8 +- lib/Target/Hexagon/HexagonSplitDouble.cpp | 40 ++-- lib/Target/Hexagon/HexagonStoreWidening.cpp | 2 +- lib/Target/Hexagon/HexagonSubtarget.cpp | 2 +- lib/Target/Hexagon/HexagonVExtract.cpp | 12 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 12 +- lib/Target/Hexagon/RDFGraph.cpp | 8 +- lib/Target/Hexagon/RDFLiveness.cpp | 4 +- lib/Target/Lanai/LanaiAsmPrinter.cpp | 2 +- lib/Target/Lanai/LanaiFrameLowering.cpp | 4 +- lib/Target/Lanai/LanaiISelLowering.cpp | 2 +- lib/Target/Lanai/LanaiInstrInfo.cpp | 2 +- lib/Target/Lanai/LanaiRegisterInfo.cpp | 2 +- lib/Target/MSP430/MSP430ISelLowering.cpp | 20 +- lib/Target/MSP430/MSP430RegisterInfo.cpp | 2 +- lib/Target/Mips/MicroMipsSizeReduction.cpp | 18 +- lib/Target/Mips/Mips16ISelDAGToDAG.cpp | 2 +- lib/Target/Mips/Mips16ISelLowering.cpp | 16 +- lib/Target/Mips/MipsAsmPrinter.cpp | 6 +- lib/Target/Mips/MipsExpandPseudo.cpp | 54 ++--- lib/Target/Mips/MipsFastISel.cpp | 2 +- lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 +- lib/Target/Mips/MipsISelLowering.cpp | 106 +++++----- lib/Target/Mips/MipsInstructionSelector.cpp | 4 +- lib/Target/Mips/MipsOptimizePICCall.cpp | 2 +- lib/Target/Mips/MipsSEFrameLowering.cpp | 48 ++--- lib/Target/Mips/MipsSEISelLowering.cpp | 116 +++++----- lib/Target/Mips/MipsSEInstrInfo.cpp | 20 +- lib/Target/Mips/MipsSERegisterInfo.cpp | 2 +- lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 +- lib/Target/PowerPC/PPCAsmPrinter.cpp | 6 +- lib/Target/PowerPC/PPCBranchSelector.cpp | 6 +- lib/Target/PowerPC/PPCFastISel.cpp | 14 +- lib/Target/PowerPC/PPCFrameLowering.cpp | 10 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 6 +- lib/Target/PowerPC/PPCISelLowering.cpp | 84 ++++---- lib/Target/PowerPC/PPCInstrInfo.cpp | 54 ++--- lib/Target/PowerPC/PPCMIPeephole.cpp | 40 ++-- lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 4 +- lib/Target/PowerPC/PPCQPXLoadSplat.cpp | 6 +- lib/Target/PowerPC/PPCReduceCRLogicals.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 32 +-- lib/Target/PowerPC/PPCTLSDynamicCall.cpp | 4 +- lib/Target/PowerPC/PPCVSXCopy.cpp | 4 +- lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 12 +- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp | 26 +-- lib/Target/Sparc/DelaySlotFiller.cpp | 10 +- lib/Target/Sparc/SparcISelDAGToDAG.cpp | 4 +- lib/Target/Sparc/SparcISelLowering.cpp | 6 +- lib/Target/Sparc/SparcInstrInfo.cpp | 4 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 12 +- lib/Target/SystemZ/SystemZElimCompare.cpp | 2 +- lib/Target/SystemZ/SystemZExpandPseudo.cpp | 4 +- lib/Target/SystemZ/SystemZFrameLowering.cpp | 2 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 78 +++---- lib/Target/SystemZ/SystemZInstrInfo.cpp | 30 +-- lib/Target/SystemZ/SystemZPostRewrite.cpp | 2 +- lib/Target/SystemZ/SystemZRegisterInfo.cpp | 14 +- lib/Target/SystemZ/SystemZShortenInst.cpp | 4 +- lib/Target/X86/X86AsmPrinter.cpp | 4 +- lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp | 2 +- lib/Target/X86/X86CallFrameOptimization.cpp | 10 +- lib/Target/X86/X86CallLowering.cpp | 2 +- lib/Target/X86/X86CmovConversion.cpp | 14 +- lib/Target/X86/X86DomainReassignment.cpp | 8 +- lib/Target/X86/X86EvexToVex.cpp | 2 +- lib/Target/X86/X86ExpandPseudo.cpp | 4 +- lib/Target/X86/X86FastISel.cpp | 4 +- lib/Target/X86/X86FixupBWInsts.cpp | 2 +- lib/Target/X86/X86FixupLEAs.cpp | 16 +- lib/Target/X86/X86FixupSetCC.cpp | 4 +- lib/Target/X86/X86FlagsCopyLowering.cpp | 8 +- lib/Target/X86/X86FloatingPoint.cpp | 6 +- lib/Target/X86/X86FrameLowering.cpp | 16 +- lib/Target/X86/X86ISelLowering.cpp | 114 +++++----- lib/Target/X86/X86InsertPrefetch.cpp | 4 +- lib/Target/X86/X86InstrInfo.cpp | 69 +++--- lib/Target/X86/X86InstructionSelector.cpp | 96 ++++----- lib/Target/X86/X86MCInstLower.cpp | 18 +- lib/Target/X86/X86OptimizeLEAs.cpp | 4 +- lib/Target/X86/X86RegisterInfo.cpp | 8 +- lib/Target/X86/X86SelectionDAGInfo.cpp | 2 +- lib/Target/X86/X86SpeculativeLoadHardening.cpp | 48 ++--- lib/Target/X86/X86WinAllocaExpander.cpp | 4 +- lib/Target/XCore/XCoreFrameLowering.cpp | 4 +- lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp | 2 +- lib/Target/XCore/XCoreISelLowering.cpp | 4 +- lib/Target/XCore/XCoreRegisterInfo.cpp | 2 +- 239 files changed, 1889 insertions(+), 1893 deletions(-)