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from 8459c546197 [RISC-V][PR target/120368] Fix 32bit shift on rv64 new 0bed343a2a6 [RISC-V] Improve (x << C1) + C2 split code

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Summary of changes: gcc/config/riscv/riscv.md | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-)