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from 788c75b81c8 [NVPTX] Enable StructuredCFG for NVPTX new 292151b43c7 [X86][BtVer2] Fix the number of uOps for horizontal operations. new eed988e3e72 [MIR] Adding support for Named Virtual Registers in MIR.

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Summary of changes: include/llvm/CodeGen/MachineRegisterInfo.h | 24 +++++++++++++++++++- include/llvm/CodeGen/TargetRegisterInfo.h | 3 ++- lib/CodeGen/MIRParser/MILexer.cpp | 14 +++++++++++- lib/CodeGen/MIRParser/MILexer.h | 3 ++- lib/CodeGen/MIRParser/MIParser.cpp | 26 ++++++++++++++++++++++ lib/CodeGen/MIRParser/MIParser.h | 2 ++ lib/CodeGen/MIRParser/MIRParser.cpp | 16 ++++++++++--- lib/CodeGen/MIRPrinter.cpp | 2 ++ lib/CodeGen/MachineOperand.cpp | 10 ++++++++- lib/CodeGen/MachineRegisterInfo.cpp | 3 ++- lib/CodeGen/TargetRegisterInfo.cpp | 14 ++++++++---- lib/Target/X86/X86ScheduleBtVer2.td | 2 ++ test/CodeGen/MIR/AArch64/namedvregs.mir | 26 ++++++++++++++++++++++ .../llvm-mca/X86/BtVer2/hadd-read-after-ld-2.s | 8 +++---- test/tools/llvm-mca/X86/BtVer2/resources-avx1.s | 16 ++++++------- 15 files changed, 144 insertions(+), 25 deletions(-) create mode 100644 test/CodeGen/MIR/AArch64/namedvregs.mir