[gcc] branch master updated (40ac6136272 -> 8a87ba0b4fe) - Tcwg-commits

22 Sep 2023


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unknown user pushed a change to branch master
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from  40ac6136272 RISC-V: Rename the test macro for math autovec test
       new  8a87ba0b4fe RISC-V: Add VLS conditional patterns support
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
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Summary of changes:
 gcc/config/riscv/autovec.md                        | 200 +++++++++------------
 gcc/config/riscv/riscv-protos.h                    |   3 +
 gcc/config/riscv/riscv-v.cc                        |  45 +++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_add-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_add-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_and-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_div-1.c  |  58 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_div-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c  |  62 +++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c |  62 +++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_max-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_max-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_min-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_min-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c  |  58 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c  |  62 +++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_not-1.c  |  62 +++++++
 .../riscv/rvv/autovec/vls/cond_shift-1.c           |  57 ++++++
 .../riscv/rvv/autovec/vls/cond_shift-2.c           |  56 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c  |  50 ++++++
 .../gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c  | 104 +++++++++++
 .../gcc.target/riscv/rvv/autovec/vls/def.h         |  70 ++++++++
 31 files changed, 2059 insertions(+), 118 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
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