This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O2_LTO in repository toolchain/ci/gcc.

from e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] adds 75fb811dfaa Verify the code used for the optimized comparison is valid [...] adds c86c99e6950 Update gcc es.po, sv.po. adds 75c24a08d69 Daily bump. adds 047811579f0 cgraphunit: Avoid code generation differences based on -w/T [...] adds a5a9400a846 if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283] adds 565ab7efbdc loop-manip: Avoid -fcompare-debug issues in create_iv [PR94285] adds 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] adds 906b3eb9df6 Improve endianess detection. adds c2211a60ff0 Fix OpenMP offload handling for target-link variables for n [...] adds 04099157691 Define __BIG_ENDIAN__ adds 8001f59c82b [testsuite,arm] target-supports.exp: Add arm_fp_dp_ok effec [...] adds 2a0eaca3e9c [testsuite,arm] cmp-2.c: Move double-precision tests to cmp-3.c adds 07f8bcc6ea9 [testsuite,arm] use arm_fp_dp_ok effective-target adds 6e771c087b1 c++: Give more expressions locations. adds 5c161741843 c++: Fix template parm with dependent type in concepts. adds fddfd3ce555 c++: Improve handling of ill-formed constraints [PR94186]. adds 75b7b7fdc45 c++: Fix wrong no post-decrement operator error in template [...] adds 0c1c8d9f137 Daily bump. adds adaf4b6c66e Test for sigsetjmp support in analyzer tests requiring that [...] adds c2133167ad5 if-conv: Delete dead stmts backwards in ifcvt_local_dce [PR94283] adds f1154b4d3c5 sccvn: Fix buffer overflow in push_partial_def [PR94300] adds 158cccea0d0 middle-end: Avoid using DECL_UID in ASM_FORMAT_PRIVATE_NAME [...] adds 5f18995e23e varasm: Fix output_constructor where a RANGE_EXPR index nee [...] adds c38daa79768 fortran: ICE using undeclared symbol in array constructor PR93484 adds c8504ebef1d testsuite: Fix up FAILs in gfortran testsuite with -fcompar [...] adds 0fb0240a051 Fix handling of --with{,out}-zstd option. adds 724ec02c2c6 Make target_clones resolver fn static if possible. adds d5ad8ee04a7 i386: Fix ix86_add_reg_usage_to_vzeroupper [PR94308] adds 780f1cfd8ee testsuite: Mention cleanup-13.c test is incompatible with - [...] adds 68c4570a4de Do not error about missing zstd unless --with-zstd. adds 83dfa06cb5c coroutines: Fix missing dereference (PR94319). adds 0fca105f8ca Fix gcc.dg/pr92301.c on targets that don't support argc/argv. adds 05c13c43990 PR tree-optimization/94131 - ICE on printf with a VLA strin [...] adds c7a252ba2d0 c++: Fix invalid -Wduplicated-cond warning [PR94265] adds 713ecb3d417 rs6000: Allow FPRs to change between SDmode and DDmode [...] adds b5228b1bc8c PR middle-end/94004 - missing -Walloca on calls to alloca d [...] adds 6e4cd3cd259 arm: Fix ICE caused by arm_gen_dicompare_reg [PR94292] adds eeb0c7c0713 Fix vector-compare-1 regressions on sh4/sh4eb caused by pat [...] adds 48817fbd761 Fix vector-compare-1 regressions on sh4/sh4eb caused by [...] adds fe4b53b2e7e testsuite: adjustments for amdgcn adds bf1fc37bb4a libstdc++: Define and use chrono::is_clock for C++20 adds e3ef371982a libstdc++ Add missing tests for std::shared_timed_mutex adds 9673d11ec53 libstdc++: Fix author in previous ChangeLog entry adds e97929e20b2 [PATCH] rs6000: vec_rlnm fix to make builtin work according to ABI adds 27f8c8c4c92 Daily bump. adds d21dff5b4fe widening_mul: restrict ops to be defined in the same basic- [...] adds 9708ca2be40 var-tracking: Mark as sp based more VALUEs [PR92264] adds 5a1706f63a2 c++: Fix a -fcompare-debug issue with DEBUG_BEGIN_STMT stmt [...] adds dab932d1519 c++: Fix up user_provided_p [PR81349] adds 10ea09ee846 gimplify: Fix -fcompare-debug differences caused by gimplif [...] adds d6730f06420 Skip test for non-x86 targets. adds da920d0c46c tree: Fix -fcompare-debug issues due to protected_set_expr_ [...] adds 40cdcddf274 Fix UNRESOLVED test-case. adds e519d644999 arm: unified syntax for libgcc when built with -Os [PR94220] adds 16948c54b75 libstdc++: Add some C++20 additions to <chrono> adds 2a1f0f64160 coroutines: Implement n4849 changes to exception handling. adds 6d85947d23a coroutines: Implement n4849 recommended symmetric transfer. adds 517f5356bb0 c++: DR1710, template keyword in a typename-specifier [PR94057] adds b1c905ba83e Update gcc .po files. adds f9c38702e96 Daily bump. adds 65937db83cd coroutines, testsuite: Fix symmetric-transfer-00-basic.C on Linux. adds 54f58e9416d c++: Remove redundant calls to type_dependent_expression_p adds 71d69548a1b c++: template keyword accepted before destructor names [PR94336] adds 06d5d63d994 modulo-sched: fix bootstrap compare-debug issue adds 72809d6fe8e c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 2eea00c518d c++: Avoid calls in non-evaluated contexts affect whether f [...] adds a76ff304f90 Fortran] Reject invalid association target (PR93363) adds a9cd2d786ad fixup: move ChangeLog entry for last Arm fix to correct file. adds 66e0e23c12d fixup: move ChangeLog entry for last Arm fix to correct file. adds 8d689cf43b5 Fix PR90332 by extending half size vector mode adds 62ede14d30f [Fortran] Fix ICE with deferred-rank arrays (PR93957) adds 917e21e8bcd tree-optimization/94352 - fix uninitialized use of curr_order adds 45cfaf9903d debug/94273 - avoid creating type DIEs for DINFO_LEVEL_TERSE adds 4d661bb7a2e analyzer: tweaks to superedge::dump adds 8f02357571a analyzer: improvements to diagnostic-manager.cc logging adds 42c63313252 analyzer: add new supergraph visualization adds 6969ac301f2 analyzer: fix malloc pointer NULL-ness adds 9dba60130dc c++: Fix ICE after ambiguous inline namespace reopen [PR94257] adds 04dd734b52d c++: avoid -Wredundant-tags on a first declaration in use [ [...] adds 038769535a8 amdgcn: refactor mode iterators adds ccacf77be55 PR c++/94098 - ICE on attribute access redeclaration adds c7fc15f54b3 [pr84733] Fix ICE popping local scope adds 52f24a9e989 PR c++/94346 - [9/10 Regression] ICE due to handle_copy_att [...] adds 54de5afb4a9 c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 19e5389debb [RS6000] PR94145, make PLT loads volatile adds 491009b609d Update gcc de.po. adds 0302a2de7f1 libstdc++: Move definition earlier in file adds ae6076b5bc1 libstdc++: Implement C++20 changes to insert iterators adds 81a8d137c22 libstdc++: Add remaining C++20 changes to iterator adaptors adds b8a28a06eaf libstdc++: Define __cpp_lib_ranges macro for C++20 adds c2781192292 Daily bump. adds 679becf175c reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329] adds c6a562de88c c: After issuing errors about array size, for error-recover [...] adds 75defde9fb5 c++: Replay errors during diagnosis of constraint satisfact [...] adds cd68edf894d c++: Respect current_constraint_diagnosis_depth in diagnose [...] adds a7ea3d2ced7 c++: requires-expression outside of a template is misevalua [...] adds 7981c06ae92 c++: Diagnose when "requires" is used instead of "requires [...] adds 3fb7f2fbd5f [Fortran] Fix result-variable handling of MODULE PROCEDURE [...] adds 7d57570b065 Patch for PR94246 adds 946a444df34 testsuite: adjust modulo-sched compare-debug tests adds 42cda3ba45f libstdc++: Fix std::reverse_iterator relational operators adds f6b2b79040d libstdc++: Fix two tests that fail in C++20 mode adds 673bb288e62 Daily bump. adds c76df72f1a9 testsuite: Split up gdc-test.exp into each subdirectory adds 46b7d819f7c Delete duplicate .align output. adds 85f6f317ec8 Fix typo in a warning related to flatten. adds afd9da8b8ad testsuite: Move C++ tests in gdc.test into own subdirectory. adds 60c254b279e testsuite: Handle more kinds of gdc.test test flags and dir [...] adds dacc7effeea doc: Update -falign-functions/-falign-loops/-falign-jumps adds 2a93fb6e962 Daily bump. adds 07c48b61a08 [RS6000] Put call cookie back in AIX/ELFv2 call patterns adds ec919cfcef8 Fix vextract* masked patterns [PR93069] adds 3a9db91bee4 Fix scan pattern of vect-8.f90 dump. adds 291aa50a631 XFAIL pr57193.c test-case. adds 5abbfd3cd36 i386: Fix up *one_cmplv*2* insn with avx512f [PR94343] adds 48c18af43fa Update bswap64-4 test for desired results adds 841e721579b RS6000 Allow builtin initialization regardless of mask adds 48e331d6382 Define TRY_EMPTY_VM_SPACE for riscv64-linux adds 1cb1986cb59 c++: Fix handling of internal fn calls in statement express [...] adds 5830f753559 c++: Fix comparison of fn() and ns::fn() [PR90711] adds 9f6abd1b03e Update gcc sv.po. adds 13a29fc5730 Daily bump. adds 3809bcd6c0e lra: set insn_code_data to NULL when freeing adds 56f0b32476c forwprop: Pattern recognize more rotates [PR94344] adds 5ea39b24122 store-merging: Allow enums during bswap recognition [PR94403] adds 1dcffc8ddc4 fold-const: Fix division folding with vector operands [PR94412] adds a27c534794d aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368] adds e81d0d9ec7a [ARM][PATCH]: Add support for MVE ACLE intrinsics polymorph [...] adds cea1fc6f67d arc: Allow more ABIs in GLIBC_DYNAMIC_LINKER adds 1ef979c6966 [ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic [...] adds d08a318b4fd arc: Cleanup compilation warning adds dc56917d111 arc: Update operand printing adds 1165109b401 amdgcn: generalize vector insn modes adds 48742e02d71 d: Use d_comdat_linkage on generated internal decl. adds e06cde870ed Library-side tests for parenthesized aggregate init adds f14b41d2712 vect: ICE: in vectorizable_load, at tree-vect-stmts.c:9173 [...] adds e8e0acbaa38 d: Use memset to fill alignment holes with zeroes. adds 331c438d5a6 Update cpplib sr.po. adds 689418b97e5 libgomp – fix handling of 'target enter data' adds 63b2923dc6f libgccjit: add new version entry point adds 1c16f7fc903 d: Add always_inline to the internal attribute table. adds 013fca64fc1 d: Merge UDAs between function prototype and definitions (PR90136) adds 73dd051894b Daily bump. adds 595f1b1274b c++: Adjust formatting. adds 76f09260b7e c++: Fix DMI with lambda 'this' capture [PR94205] adds bd0f22a8d5c Fix PR94043 by making vect_live_op generate lc-phi adds 142d68f50b4 Fix typo in a macro usage. adds 9ecb3ecc8cc objsz: Don't call replace_uses_by on SSA_NAME_OCCURS_IN_ABN [...] adds d3ee88fdb4e Clear me from patch ownership. adds 0c9a8a8c103 fortran : FAIL: gfortran.dg/pr93365.f90 PR94386 adds e899d4b7125 Add testcase for already fixed PR [PR94436] adds 032f2366a4c rs6000: Make code questionably using r2 not ICE (PR94420) adds dd5da571731 doc: Fix a typo in the documentation of the copy attribute adds 43d011eb054 Whoops, forgot the changelog adds b60bd122dc7 doc: Fix typo adds 7546463b9f7 subreg: Fix PR94123, SVN r273240 causes gcc.target/powerpc/ [...] adds a96f1c38a78 analyzer: handle compound assignments [PR94378] adds 6c557ba5380 libstdc++: Move "free books" list from fsf.org to gnu.org adds fb25041e11d d: Fix gdc.dg/pr92216.d FAILs on 32-bit targets adds 918b89b7623 d: Fix new tests gdc.dg/pr93038.d and gdc.dg/pr93038b.d in [...] adds 25839b6af9f Daily bump. adds bf1f6d8819a fortran: ICE equivalence with an element of an array PR94030 adds 2c54eab5a30 fortran : ICE in gfc_resolve_findloc PR93498 adds b7a98f48e06 S/390: Remove superfluous commutative constraint modifiers adds 224efaf7e1e [Fortran] Fix error cleanup of select rank (PR93522) adds c1effaa209f libstdc++-v3/test: Better skip for "use_service.cc" adds ff825b81583 [ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317). adds 66e327517b1 aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] adds df562b12d90 aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] adds 2c0fa3ecf70 cselib: Reuse VALUEs on sp adjustments [PR92264] adds 86c92411320 params: Decrease -param=max-find-base-term-values= default [...] adds d4ed2cd13d0 sra/doc: Document param sra-max-propagations adds 68cbee9bf53 Fix up -Wliteral-suffix warning on mti-linux.h adds 81ce375d1fd Fix PR94401 by considering reverse overrun adds 879bc686a0a doc: RISC-V: Update binutils requirement to 2.30 adds 54af95767e8 debug/94450 - remove DW_TAG_imported_unit generated in LTRA [...] adds 75efe9cb1f8 c/94392 - only enable -ffinite-loops for C++ adds b90061c6ec0 Prevent IPA-SRA from creating calls to local comdats (PR 92676) adds 3ab216a4d2f [Fortran] Resolve formal args before checking DTIO adds 0cd74f35889 Fix fortran/85982 ICE in resolve_component. adds a950bb6e952 Fix check_effective_target_sigsetjmp for glibc targets. adds 63f56527335 Fix some comment typos in alias.c. adds 535ce76acbe Daily bump. adds b749b5ec58a S/390 zTPF: Handle skip trace addresses when unwinding adds 55a7380213a ICF: compare type attributes for gimple_call_fntypes. adds 4441ecedc3d Fix PR94443 with gsi_insert_seq_before [PR94443] adds 2b1e849b35b Revert "[nvptx, libgomp] Update pr85381-{2,4}.c test-cases" [...] adds 24fe8c8e338 libstdc++: Fix std::to_address for debug iterators (PR 93960) adds 1dff18a181b amdgcn: Support unordered floating-point comparison operators adds fa4aab7f840 Improve svn-rev to search for pattern at line beginning. adds ef6631051d4 middle-end/94465 - handle released SSA names in array_ref_l [...] adds 53161358180 AArch64: Fix options canonicalization for assembler adds 3b6e79ae0c3 arm: Do not process rest of MVE header file after unsupport [...] adds a87cd913ae2 arm: MVE: Fix unintended change to tests adds 51ecad3c032 c++: Add test for PR c++/93211 adds b8020a5aafd i386: Fix vph{add,subs?}[wd] 256-bit AVX2 RTL patterns [PR94460] adds bcafd8748cf c++: alias template and parameter packs (PR91966). adds a13d6ec867e i386: Fix up handling of OPTION_MASK_ISA_MMX builtins [PR94461] adds b949f8e2acb Fix va-arg-22.c at -O1 on m32r. adds bbcdf9bb3fd x86: Mark scratch operand in ssse3_pshufbv8qi3 as earlyclobber adds 710d54ed4e3 libgcc: avoid mmap/munmap hooks in split-stack code on GNU/Linux adds 0c809f727cd openmp: Fix ICE on #pragma omp parallel master in template [...] adds 7f26e60c260 Fix stdarg-3 regression on xstormy16 port adds 78e27649095 Daily bump. adds aae5d08a8d4 c++: Fix further protected_set_expr_location related -fcomp [...] adds bab8d9625f4 cselib: Don't consider SP_DERIVED_VALUE_P values as useless [...] adds 2523d721cfc ipa: Fix wrong code with failed propagation to builtin_cons [...] adds 9f143008c73 c++: Fix reuse of class constants [PR94453] adds f1ad7bac76b c++: Fix invalid pointer-to-member in requires [PR67825] adds 21e28527130 Fix previous commit. adds 37244b217a7 c++: Fix constexpr evaluation of self-modifying CONSTRUCTOR [...] adds 49a86fce1a8 c++: Refrain from using replace_placeholders in constexpr e [...] adds 75c8d6e54a1 c++: Mangling of dependent conversions [PR91377] adds 458ca332d10 libgcc: only use __mmap if glibc >- 2.26 adds 0be9efad938 debug: Improve debug info of c++14 deduced return type [PR94459] adds 705510a708d Daily bump. adds 971c3d0ea28 Microblaze: Modified trap instruction There is a bug in tra [...] adds a2ccd780271 Microblaze: Fixed missing save of r18 in fast_interrupt. Re [...] adds 999611489d7 Minor doc fix for ISO C90 adds 3b35e71d45a coroutines, testsuite: Renumber two tests (NFC). adds 2a1a0c8c0db libstdc++: Refer to Git documentation adds c72a1b6f8b2 Daily bump. adds f84aded848f c++: Fix crash in gimplifier with paren init of aggregates [...] adds b696698767b libstdc++: Make string_view::copy usable in constant expres [...] adds e83714f65d1 lra: Stop eh_return data regs being incorrectly marked live [...] adds 130f703da0c skip gcc.target/arm/div64-unwinding.c on vxworks_kernel targets adds d42a2e465d8 Fix fortran/93686 -- ICE matching data statements with deri [...] adds 6a38c697c6c Update cpplib eo.po. adds e0fd9ce257c Update gcc sv.po. adds 8662d059343 cselib: Fix endless cselib loop on (plus:P (reg) (const_int 0)) adds 5ff06d762a8 libatomic/test: Fix compilation for build sysroot adds 749bd22ddc5 libgomp/test: Remove a build sysroot fix regression adds 52fa80f853c libgo: update to almost the 1.14.2 release adds 93a49d2d229 Daily bump. adds 467fc7c83ab c++: Fix ICE with implicit operator== [PR94462] adds bee27152f7e i386: Fix emit_reduc_half on V{64Q,32H}Imode [PR94500] adds 42867b875c3 RTEMS: Delete useless mcpu=8540 multilib adds 30d26118f96 d: Always set ASM_VOLATILE_P on asm statements (PR94425) adds 7a6588fe654 aarch64: Fix {ash[lr],lshr}<mode>3 expanders [PR94488] adds 4df50a059fb openmp: Fix parallel master error recovery [PR94512] adds d51af82b4cf i386: Fix V{64QI,32HI}mode constant permutations [PR94509] adds 23f1f679141 c++: Fix usage of CONSTRUCTOR_PLACEHOLDER_BOUNDARY inside a [...] adds 434fe1a4092 S/390: Fix layout of struct sigaction_t adds 0f3cc1b3994 arm: MVE: Fix polymorphism for scalars and constants adds 3ce755a80d1 arm: MVE: Do not use typeof for pointer parameters adds b094133c1c5 arm: MVE: Fix constant load pattern adds 9ce780efc4a arm: MVE: Fix v[id]wdup's adds 094bc16bb41 arm: MVE Don't use lsll for 32-bit shifts scalar adds d2ce75fef9f arm: MVE Fix immediate constraints on some vector instructions adds 302b6836280 arm: MVE: Fix vec extracts to memory adds c431634b2f2 arm: MVE: make sure we only use the Arm namespace variant o [...] adds f6d7098d761 arm: MVE: Fix -Wall testisms adds ff0597dcd99 arm: MVE: Fixes for pointers used in intrinsics for c++ adds 6a90680bfff arm: MVE: Add C++ polymorphism and fix some more issues adds 89b01e86ff8 coroutines, ensure placeholder var is properly declared. adds c104e8f1b67 libstdc++: Restore ability to use <charconv> in C++14 (PR 94520) adds 2daa92ac4b5 aarch64: Fix {ash[lr],lshr}<mode>3 expanders [PR94488] adds 57391ddaf39 Fix PR fortran/93871 and re-implement degree-valued trigono [...] adds 3d947f1f271 middle-end/94479 - fix gimplification of address adds 50c7853216e libgcc: use syscall rather than __mmap/__munmap adds 88e508f9f11 S/390: Fix PR91628 adds c23c899aedf combine: Fix split_i2i3 ICE [PR94291] adds 31449cf8e11 c++: ICE on invalid concept placeholder [PR94481]. adds 14162197fd4 Fix a variety of testsuite failures on the H8 after recent [...] adds 7e5367f34d7 Daily bump. adds f1a6150ecb7 libphobos: Merge upstream phobos fb4f6a713 adds 845d451e1f7 c++: requires-expression and tentative parse [PR94480] adds 38c3017f257 libphobos: Always build with warning flags enabled adds 13e41d8b9d3 [C/C++, OpenACC] Reject vars of different scope in acc decl [...] adds 54cb3baa82d Undo accidental commit to omp-grid.c adds 4ed1ff7ecbf HSA: omp-grid.c – access proper clause code adds 70b55b25aa1 postreload: Fix autoinc handling in reload_cse_move2add [PR94516] adds 542f73539db update polytypes.c -flax-vector-conversions msg adds a6479aa4c05 c++: ICE with defaulted comparison operator [PR94478] adds 4cf6b06cb5b c++: Further fix for -fsanitize=vptr [PR94325] adds 975e6670c42 arm: CLI for Custom Datapath Extension (CDE) adds 12f55e030ed c++: Function type and parameter type disagreements [PR92010] adds 07b9bfd02b8 arm: CDE intrinsics using FPU/MVE S/D registers adds a5f3c89e1b7 [Arm] Implement scalar Custom Datapath Extension intrinsics adds 78bf9163764 [Arm] Implement CDE intrinsics for MVE registers. adds ef684c78273 [Arm] Implement CDE predicated intrinsics for MVE registers adds e18cd376e0d libstdc++: Add comparison operators to <charconv> result types adds 70df40cab6f Allow new/delete operator deletion only for replaceable. adds e4b84abcc46 require tls_runtime for tls execution test adds ef389dadd4f libstdc++: Add comparison operators to types from Numerics clause adds faa0817311f Move gfortran.dg/dec_math_5.f90 to ./ieee/ adds 8bf5faa9c46 i386: Don't use AVX512F integral masks for V*TImode [PR94438] adds c5f37965396 x86: Insert ENDBR if function will be called indirectly adds 7dbfcb91a87 add missing fp16 options adds dd9ca9d770a rtl-optimization/93946 - fix TBAA for redundant store remov [...] adds 77d6dfc9298 c++: Fix ICE-on-invalid with lambda template [PR94507] adds 08d1e7a5aab openacc: Fix up declare-pr94120.C testcase [PR94533] adds 6c9a711575d testsuite: Fix up pr94314*.C tests [PR94314] adds f52eb4f9889 vect: Fix up lowering of TRUNC_MOD_EXPR by negative constan [...] adds d0cc1b79b39 cselib, reload: Fix cselib ICE on m68k/microblaze [PR94526] adds 72c136c9007 libphobos: Remove --enable-unix configure option. adds 48242b2c3ac rs6000: Link with libc128.a for long-double-128. adds 6e286c8df45 libphobos: Remove --enable-thread-lib configure option. adds c0dbfbd763a libphobos: Add --enable-libphobos-checking configure option adds 4049edc23e4 Daily bump. adds e7c4084d11b [testsuite] Fix PR94079 by respecting vect_hw_misalign [PR94079] adds b4e8cd08326 Whoops, fix wrong PR number in the changelog adds fe1837143f1 Require pthread effective target for test case using -pthre [...] adds 926d39c3816 coroutines: Add cleanups, where required, to statements wit [...] adds ed80b385418 Add unsigned type iv_cand for iv_use with non mode-precision type adds af19e4d0e23 PR target/94530 adds bb40460646c testsuite/93369 - use -shared to avoid issue with ODR violation adds 7ed2d6cbd09 testsuite: Tweak check-function-bodies interface adds f60979edbfc Avoid g++.dg/lto/alias-4_0.C test failure on ARM [PR91322] adds 14828900469 Fix typo in my previous change. adds 830c5724287 c++: Fix wrong paren-init of aggregates interference [PR93790] adds 2111d5406a4 sra: Fix sra_modify_expr handling of partial writes (PR 94482) adds f9d09df0f35 Merge top-level configury changes from gdb adds 93674a72309 [testsuite] scanasm.exp: Fix target-selector handling in ch [...] adds 8b5bc7d12de [testsuite][arm] Fix cmse-15.c expected output adds bbb0de4a4ac libphobos: Remove --enable-druntime-gc configure option. adds a4d2774c9c1 [Arm] Allow the use of arm_cde.h for C++ adds 5002dae3df4 aarch64: Add a separate "SVE sizeless type" attribute adds 38e62001c57 aarch64: Add support for arm_sve_vector_bits adds 33c45e51b49 cselib, var-tracking: Improve debug info after the cselib s [...] adds 07432a807ed MSP430: Indiciate that the epilogue_helper insn does not fallthru adds 5b074864f8c libstdc++: Add comparison operators to std::unique_ptr adds 3fd1c229ad1 libstdc++: Implement LWG 3324 for [cmp.alg] function object [...] adds ef529765234 c++: constexpr static data member instantiation [PR94523] adds 44facdb79f2 PR fortran/87923 -- fix ICE when resolving I/O tags and sim [...] adds fef3d8b4a07 Daily bump. adds d09f80ae014 compiler: look up composite literal keys in the global namespace adds d79a22eddc6 libgo: update to final 1.14.2 release adds 6c4a05f251a Simplify co_await_expander. adds 7478addd84a libphobos: Use libdruntime as a convenience library for libphobos. adds ff3f862b451 Handle 'omp declare target' attribute set for both OpenACC [...] adds 6b816a5f0ed Add 'dg-do run' to 'libgomp.fortran/target-enter-data-1.f90' adds be9862dd969 Test cases for mixed structured/dynamic data lifetimes with [...] adds ecc66362ee5 Fix UNRESOLVED testcase gfortran.dg/asynchronous_5.f03. adds e26bd694c79 Fix typo in gfortran.dg/asynchronous_5.f03 from last commit. adds 62c25d7adb1 c++: make __is_constructible work with paren-init of aggrs [...] adds 0666767eb4c coroutines: Revise await expansions [PR94528] adds a02558a3953 Correct PR numbers in the last Changelog. adds 47539a4acef Daily bump. adds a615ea71bc8 cselib: Mark the cselib_record_sp_cfa_base_equiv VALUE as p [...] adds bb87d5cc77d testsuite: Fix up pr94482.c testcase [PR94482]

No new revisions were added by this update.

Summary of changes: ChangeLog | 10 + Makefile.def | 16 + Makefile.in | 933 + configure | 39 +- configure.ac | 36 +- contrib/ChangeLog | 5 + contrib/gcc-git-customization.sh | 2 +- gcc/ChangeLog | 8902 +++- gcc/DATESTAMP | 2 +- gcc/alias.c | 14 +- gcc/analyzer/ChangeLog | 196 + gcc/analyzer/analyzer.h | 1 + gcc/analyzer/checker-path.cc | 1 + gcc/analyzer/constraint-manager.cc | 1 + gcc/analyzer/diagnostic-manager.cc | 50 +- gcc/analyzer/diagnostic-manager.h | 32 + gcc/analyzer/engine.cc | 287 +- gcc/analyzer/exploded-graph.h | 31 +- gcc/analyzer/program-point.cc | 1 + gcc/analyzer/program-state.cc | 3 +- gcc/analyzer/region-model.cc | 638 +- gcc/analyzer/region-model.h | 171 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/analyzer/state-purge.cc | 21 +- gcc/analyzer/state-purge.h | 5 +- gcc/analyzer/supergraph.cc | 56 +- gcc/analyzer/supergraph.h | 19 +- gcc/asan.c | 7 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 41 + gcc/c-family/c-attribs.c | 35 +- gcc/c-family/c-common.c | 13 +- gcc/c-family/c-opts.c | 4 + gcc/c-family/c-warn.c | 5 + gcc/c-family/c.opt | 4 + gcc/c/ChangeLog | 59 + gcc/c/c-decl.c | 65 +- gcc/c/c-fold.c | 9 + gcc/c/c-parser.c | 63 +- gcc/c/c-tree.h | 15 +- gcc/c/c-typeck.c | 5 +- gcc/calls.c | 82 +- gcc/cfgexpand.c | 2 +- gcc/cfgloop.h | 4 + gcc/cfgloopmanip.c | 1 + gcc/cgraph.c | 97 +- gcc/cgraph.h | 17 +- gcc/cgraphunit.c | 32 +- gcc/combine.c | 42 +- gcc/common.opt | 2 +- gcc/common/config/aarch64/aarch64-common.c | 17 +- gcc/common/config/arm/arm-common.c | 3 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-c.c | 2 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd.md | 100 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 104 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 885 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/aarch64/atomics.md | 5 +- gcc/config/aarch64/constraints.md | 7 + .../aarch64/falkor-tag-collision-avoidance.c | 5 +- gcc/config/aarch64/iterators.md | 3 +- gcc/config/arc/arc.c | 8 +- gcc/config/arc/arc.h | 6 +- gcc/config/arc/linux.h | 3 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 905 +- gcc/config/arm/arm-builtins.h | 35 + gcc/config/arm/arm-c.c | 131 + gcc/config/arm/arm-cpus.in | 40 +- gcc/config/arm/arm-protos.h | 3 +- gcc/config/arm/arm.c | 292 +- gcc/config/arm/arm.h | 87 +- gcc/config/arm/arm.md | 107 +- gcc/config/arm/arm_cde.h | 176 + gcc/config/arm/arm_cde_builtins.def | 58 + gcc/config/arm/arm_mve.h | 42125 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 906 + gcc/config/arm/arm_mve_types.h | 1490 + gcc/config/arm/constraints.md | 54 +- gcc/config/arm/iterators.md | 34 +- gcc/config/arm/mve.md | 11416 +++++ gcc/config/arm/neon.md | 75 +- gcc/config/arm/predicates.md | 87 +- gcc/config/arm/t-arm | 5 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/types.md | 18 +- gcc/config/arm/unspecs.md | 6 + gcc/config/arm/vec-common.md | 116 +- gcc/config/arm/vfp.md | 199 +- gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/gcn/gcn-valu.md | 2113 +- gcc/config/gcn/gcn.c | 15 + gcc/config/gcn/gcn.h | 4 + gcc/config/gcn/gcn.md | 2 + gcc/config/gcn/predicates.md | 2 +- gcc/config/h8300/h8300.md | 1 + gcc/config/host-linux.c | 2 + gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386-builtin.def | 126 +- gcc/config/i386/i386-builtins.c | 37 +- gcc/config/i386/i386-expand.c | 95 +- gcc/config/i386/i386-features.c | 13 +- gcc/config/i386/i386.c | 6 +- gcc/config/i386/i386.h | 5 +- gcc/config/i386/i386.md | 25 +- gcc/config/i386/predicates.md | 5 - gcc/config/i386/sse.md | 89 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/m32r/m32r.c | 2 +- gcc/config/microblaze/microblaze.c | 2 +- gcc/config/microblaze/microblaze.md | 2 +- gcc/config/mips/mti-linux.h | 2 +- gcc/config/msp430/msp430.c | 4 +- gcc/config/msp430/msp430.md | 4 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/pa/pa.c | 1 - gcc/config/pa/pa.h | 1 + gcc/config/rs6000/aix61.h | 1 + gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/altivec.h | 2 +- gcc/config/rs6000/constraints.md | 11 + gcc/config/rs6000/rs6000-c.c | 2 +- gcc/config/rs6000/rs6000-call.c | 28 - gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 57 +- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 136 +- gcc/config/rs6000/t-rtems | 1 - gcc/config/s390/vector.md | 80 +- gcc/config/s390/vx-builtins.md | 78 +- gcc/config/sh/sh.md | 8 +- gcc/config/stormy16/stormy16.c | 12 +- gcc/configure | 13 +- gcc/configure.ac | 9 +- gcc/cp/ChangeLog | 527 + gcc/cp/call.c | 34 +- gcc/cp/class.c | 10 +- gcc/cp/constexpr.c | 405 +- gcc/cp/constraint.cc | 280 +- gcc/cp/coroutines.cc | 768 +- gcc/cp/cp-gimplify.c | 72 +- gcc/cp/cp-tree.h | 8 +- gcc/cp/cvt.c | 11 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/decl.c | 70 +- gcc/cp/decl2.c | 3 +- gcc/cp/error.c | 35 +- gcc/cp/except.c | 5 +- gcc/cp/expr.c | 22 +- gcc/cp/init.c | 2 + gcc/cp/logic.cc | 8 +- gcc/cp/mangle.c | 1 + gcc/cp/method.c | 59 +- gcc/cp/name-lookup.c | 65 +- gcc/cp/parser.c | 483 +- gcc/cp/pt.c | 218 +- gcc/cp/semantics.c | 9 +- gcc/cp/tree.c | 44 +- gcc/cp/typeck2.c | 20 +- gcc/cse.c | 14 +- gcc/cselib.c | 334 +- gcc/cselib.h | 2 + gcc/d/ChangeLog | 107 + gcc/d/d-attribs.cc | 43 +- gcc/d/d-codegen.cc | 44 - gcc/d/d-lang.cc | 81 +- gcc/d/d-spec.cc | 14 +- gcc/d/d-target.cc | 2 +- gcc/d/d-tree.h | 11 +- gcc/d/decl.cc | 66 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/iasmgcc.c | 30 +- gcc/d/dmd/module.h | 1 + gcc/d/expr.cc | 22 +- gcc/d/modules.cc | 2 +- gcc/d/toir.cc | 5 +- gcc/d/typeinfo.cc | 49 +- gcc/d/types.cc | 89 +- gcc/ddg.c | 169 +- gcc/ddg.h | 3 - gcc/doc/extend.texi | 6 +- gcc/doc/install.texi | 28 +- gcc/doc/invoke.texi | 36 +- gcc/doc/sourcebuild.texi | 47 +- gcc/doc/tm.texi | 4 +- gcc/dse.c | 57 +- gcc/dwarf2out.c | 108 +- gcc/fold-const.c | 17 +- gcc/fortran/ChangeLog | 182 + gcc/fortran/arith.c | 12 +- gcc/fortran/array.c | 2 +- gcc/fortran/check.c | 4 + gcc/fortran/class.c | 2 +- gcc/fortran/decl.c | 51 +- gcc/fortran/expr.c | 46 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/gfortran.h | 16 +- gcc/fortran/interface.c | 4 +- gcc/fortran/intrinsic.c | 193 +- gcc/fortran/intrinsic.h | 12 +- gcc/fortran/io.c | 858 +- gcc/fortran/iresolve.c | 256 +- gcc/fortran/match.c | 13 +- gcc/fortran/module.c | 4 +- gcc/fortran/resolve.c | 66 +- gcc/fortran/simplify.c | 300 +- gcc/fortran/trans-array.c | 6 +- gcc/fortran/trans-expr.c | 2 +- gcc/fortran/trans-intrinsic.c | 196 + gcc/fortran/trans-types.c | 2 +- gcc/fortran/trigd_fe.inc | 50 + gcc/gimple-fold.c | 22 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/gimple-ssa-sprintf.c | 10 +- gcc/gimple-ssa-store-merging.c | 9 +- gcc/gimple-ssa-warn-alloca.c | 65 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/gimple.c | 6 +- gcc/gimple.h | 16 +- gcc/gimplify.c | 39 +- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/expressions.cc | 14 +- gcc/graphviz.cc | 44 +- gcc/graphviz.h | 6 + gcc/hsa-common.c | 2 +- gcc/input.c | 4 +- gcc/ipa-cp.c | 13 +- gcc/ipa-fnsummary.c | 48 +- gcc/ipa-icf-gimple.c | 6 + gcc/ipa-icf.c | 4 + gcc/ipa-inline-transform.c | 9 +- gcc/ipa-inline.c | 4 + gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-predicate.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/ipa-prop.h | 2 +- gcc/ipa-split.c | 2 +- gcc/ipa-sra.c | 38 +- gcc/ira-costs.c | 2 +- gcc/jit/ChangeLog | 24 + gcc/jit/docs/topics/compatibility.rst | 33 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/jit/libgccjit++.h | 22 + gcc/jit/libgccjit.c | 46 + gcc/jit/libgccjit.h | 16 + gcc/jit/libgccjit.map | 9 +- gcc/langhooks.c | 5 +- gcc/langhooks.h | 2 +- gcc/lower-subreg.c | 3 +- gcc/lra-constraints.c | 24 +- gcc/lra-lives.c | 6 + gcc/lra-spills.c | 12 +- gcc/lra.c | 5 +- gcc/lto-section-in.c | 1 + gcc/lto-streamer-in.c | 1 + gcc/lto-streamer-out.c | 83 +- gcc/lto-streamer.h | 1 + gcc/lto/ChangeLog | 28 + gcc/lto/lto-common.c | 1 + gcc/lto/lto-lang.c | 3 +- gcc/lto/lto.c | 13 +- gcc/modulo-sched.c | 13 +- gcc/multiple_target.c | 4 - gcc/omp-general.c | 13 + gcc/omp-grid.c | 4 +- gcc/omp-offload.c | 14 +- gcc/optinfo-emit-json.cc | 2 +- gcc/opts.c | 30 +- gcc/params.opt | 6 +- gcc/po/ChangeLog | 30 + gcc/po/be.po | 15546 ++++--- gcc/po/da.po | 16726 ++++---- gcc/po/de.po | 15296 ++++--- gcc/po/el.po | 15654 ++++--- gcc/po/es.po | 15527 ++++--- gcc/po/fi.po | 17525 ++++---- gcc/po/fr.po | 15310 ++++--- gcc/po/gcc.pot | 15239 ++++--- gcc/po/hr.po | 15206 ++++--- gcc/po/id.po | 17084 ++++---- gcc/po/ja.po | 16929 ++++---- gcc/po/nl.po | 16172 +++---- gcc/po/ru.po | 15477 ++++--- gcc/po/sr.po | 16946 ++++---- gcc/po/sv.po | 16223 ++++--- gcc/po/tr.po | 17101 ++++---- gcc/po/uk.po | 17022 ++++---- gcc/po/vi.po | 15520 ++++--- gcc/po/zh_CN.po | 17326 ++++---- gcc/po/zh_TW.po | 17429 ++++---- gcc/postreload.c | 27 +- gcc/read-rtl-function.c | 6 +- gcc/reload1.c | 5 +- gcc/rtl.c | 2 +- gcc/rtl.h | 1 + gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/simplify-rtx.c | 51 + gcc/spellcheck.c | 2 +- gcc/symtab.c | 20 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 6447 ++- gcc/testsuite/c-c++-common/attr-copy.c | 43 + gcc/testsuite/c-c++-common/goacc-gomp/pr93465-1.c | 56 + gcc/testsuite/c-c++-common/goacc/declare-pr94120.c | 23 + .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/c-c++-common/pr94385.c | 12 + .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + gcc/testsuite/g++.dg/abi/mangle75.C | 13 + gcc/testsuite/g++.dg/concepts/diagnostic1.C | 1 + gcc/testsuite/g++.dg/concepts/diagnostic2.C | 2 +- gcc/testsuite/g++.dg/concepts/diagnostic5.C | 43 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic7.C | 11 + gcc/testsuite/g++.dg/concepts/diagnostic8.C | 6 + gcc/testsuite/g++.dg/concepts/pr84330.C | 2 +- gcc/testsuite/g++.dg/concepts/pr94252.C | 27 + gcc/testsuite/g++.dg/conversion/op7.C | 22 + .../g++.dg/coroutines/co-await-syntax-10.C | 40 + .../g++.dg/coroutines/co-await-syntax-11.C | 205 + gcc/testsuite/g++.dg/coroutines/pr94528.C | 64 + ...late-traits.C => co-await-16-template-traits.C} | 0 ...e-comp-ref.C => co-await-17-capture-comp-ref.C} | 0 .../coroutines/torture/co-ret-09-bool-await-susp.C | 44 +- .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- .../torture/exceptions-test-01-n4849-a.C | 213 + .../torture/symmetric-transfer-00-basic.C | 111 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + .../g++.dg/cpp0x/lambda/lambda-constexpr1.C | 28 + gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 + gcc/testsuite/g++.dg/cpp0x/variadic-alias2.C | 103 + gcc/testsuite/g++.dg/cpp1y/alias-decl1.C | 9 + gcc/testsuite/g++.dg/cpp1y/alias-decl2.C | 8 + gcc/testsuite/g++.dg/cpp1y/alias-decl3.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi2.C | 20 + gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi3.C | 19 + gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi4.C | 21 + gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi5.C | 22 + gcc/testsuite/g++.dg/cpp1y/constexpr-static1.C | 10 + gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C | 15 + gcc/testsuite/g++.dg/cpp1y/pr79937-5.C | 42 + gcc/testsuite/g++.dg/cpp1y/pr90996.C | 17 + gcc/testsuite/g++.dg/cpp1y/pr94066-2.C | 19 + gcc/testsuite/g++.dg/cpp1y/pr94066-3.C | 16 + gcc/testsuite/g++.dg/cpp1y/pr94066.C | 18 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/cpp1z/lambda-this4.C | 13 + gcc/testsuite/g++.dg/cpp1z/lambda-this5.C | 11 + gcc/testsuite/g++.dg/cpp1z/lambda-this6.C | 12 + gcc/testsuite/g++.dg/cpp1z/pr81349.C | 29 + gcc/testsuite/g++.dg/cpp2a/concepts-iconv1.C | 1 + gcc/testsuite/g++.dg/cpp2a/concepts-nonbool1.C | 20 + gcc/testsuite/g++.dg/cpp2a/concepts-nonbool2.C | 11 + gcc/testsuite/g++.dg/cpp2a/concepts-placeholder2.C | 9 + gcc/testsuite/g++.dg/cpp2a/concepts-pmf1.C | 22 + gcc/testsuite/g++.dg/cpp2a/concepts-pr67825.C | 2 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires1.C | 4 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires18.C | 2 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires2.C | 12 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires21.C | 7 + gcc/testsuite/g++.dg/cpp2a/concepts-requires5.C | 2 +- gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C | 18 + gcc/testsuite/g++.dg/cpp2a/lambda-generic7.C | 10 + gcc/testsuite/g++.dg/cpp2a/lambda-uneval11.C | 10 + gcc/testsuite/g++.dg/cpp2a/paren-init22.C | 15 + gcc/testsuite/g++.dg/cpp2a/paren-init23.C | 19 + gcc/testsuite/g++.dg/cpp2a/paren-init24.C | 26 + gcc/testsuite/g++.dg/cpp2a/paren-init25.C | 25 + gcc/testsuite/g++.dg/cpp2a/spaceship-eq9.C | 17 + gcc/testsuite/g++.dg/cpp2a/spaceship-err4.C | 7 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/debug/pr94272.C | 14 + gcc/testsuite/g++.dg/debug/pr94273.C | 4 + gcc/testsuite/g++.dg/debug/pr94281.C | 11 + gcc/testsuite/g++.dg/debug/pr94323.C | 13 + gcc/testsuite/g++.dg/debug/pr94459.C | 58 + gcc/testsuite/g++.dg/ext/attr-access-2.C | 88 + gcc/testsuite/g++.dg/ext/is_constructible5.C | 16 + gcc/testsuite/g++.dg/ext/pr94197.C | 74 + gcc/testsuite/g++.dg/ext/stmtexpr15.C | 2 +- gcc/testsuite/g++.dg/goacc/declare-pr94120.C | 30 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/g++.dg/gomp/pr94477.C | 18 + gcc/testsuite/g++.dg/gomp/pr94512.C | 18 + gcc/testsuite/g++.dg/init/aggr14.C | 14 + gcc/testsuite/g++.dg/lookup/pr84733.C | 21 + gcc/testsuite/g++.dg/lookup/pr94257.C | 16 + gcc/testsuite/g++.dg/lto/alias-4_0.C | 8 +- gcc/testsuite/g++.dg/lto/pr64076_0.C | 4 + gcc/testsuite/g++.dg/lto/pr64076_1.C | 2 +- gcc/testsuite/g++.dg/opt/pr94223.C | 5 + gcc/testsuite/g++.dg/opt/pr94441.C | 16 + gcc/testsuite/g++.dg/opt/pr94468.C | 57 + gcc/testsuite/g++.dg/other/pr94326.C | 19 + gcc/testsuite/g++.dg/other/pr94339.C | 11 + gcc/testsuite/g++.dg/parse/error26.C | 2 +- gcc/testsuite/g++.dg/parse/missing-template1.C | 4 +- gcc/testsuite/g++.dg/parse/template3.C | 5 +- gcc/testsuite/g++.dg/pr93674.C | 16 + gcc/testsuite/g++.dg/pr94314-2.C | 26 + gcc/testsuite/g++.dg/pr94314-3.C | 55 + gcc/testsuite/g++.dg/pr94314.C | 85 + gcc/testsuite/g++.dg/template/array33.C | 63 + gcc/testsuite/g++.dg/template/array34.C | 63 + gcc/testsuite/g++.dg/template/defarg22.C | 13 + gcc/testsuite/g++.dg/template/dependent-name10.C | 18 + gcc/testsuite/g++.dg/template/dependent-name11.C | 15 + gcc/testsuite/g++.dg/template/dependent-name12.C | 7 + gcc/testsuite/g++.dg/template/dependent-name13.C | 8 + gcc/testsuite/g++.dg/template/dependent-name14.C | 38 + gcc/testsuite/g++.dg/template/dependent-name5.C | 2 - gcc/testsuite/g++.dg/template/dependent-name7.C | 9 + gcc/testsuite/g++.dg/template/dependent-name8.C | 9 + gcc/testsuite/g++.dg/template/dependent-name9.C | 9 + gcc/testsuite/g++.dg/template/dr1710-2.C | 10 + gcc/testsuite/g++.dg/template/dr1710.C | 9 + gcc/testsuite/g++.dg/template/dr1794.C | 14 + gcc/testsuite/g++.dg/template/dr314.C | 15 + gcc/testsuite/g++.dg/template/error4.C | 3 +- gcc/testsuite/g++.dg/template/koenig11.C | 11 + gcc/testsuite/g++.dg/template/meminit2.C | 4 +- gcc/testsuite/g++.dg/template/template-keyword2.C | 5 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/torture/pr94216.C | 45 + gcc/testsuite/g++.dg/torture/pr94303.C | 17 + gcc/testsuite/g++.dg/tree-ssa/pr93940.C | 39 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.dg/tree-ssa/pr94403.C | 37 + gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/ubsan/vptr-15.C | 14 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wduplicated-cond1.C | 16 + gcc/testsuite/g++.dg/warn/Wmismatched-tags-3.C | 14 + gcc/testsuite/g++.dg/warn/Wmismatched-tags-4.C | 141 + gcc/testsuite/g++.dg/warn/Wmismatched-tags-5.C | 117 + gcc/testsuite/g++.dg/warn/Wmismatched-tags-6.C | 29 + gcc/testsuite/g++.dg/warn/Wnoexcept1.C | 2 +- gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 + gcc/testsuite/g++.dg/warn/Wredundant-tags-3.C | 6 +- gcc/testsuite/g++.dg/warn/Wredundant-tags-6.C | 91 + gcc/testsuite/g++.dg/warn/Wredundant-tags-7.C | 25 + gcc/testsuite/g++.old-deja/g++.pt/crash38.C | 6 +- gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/g++.target/arm/cde_mve.C | 10 + gcc/testsuite/g++.target/arm/mve.exp | 49 + gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/pr94144.c | 18 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + gcc/testsuite/gcc.c-torture/compile/pr94238.c | 22 + gcc/testsuite/gcc.c-torture/compile/pr94488.c | 22 + gcc/testsuite/gcc.c-torture/execute/pr94412.c | 28 + gcc/testsuite/gcc.c-torture/execute/pr94524-1.c | 19 + gcc/testsuite/gcc.c-torture/execute/pr94524-2.c | 25 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/Walloca-larger-than-3.c | 38 + gcc/testsuite/gcc.dg/Walloca-larger-than-3.h | 9 + gcc/testsuite/gcc.dg/Wvla-larger-than-4.c | 30 + .../gcc.dg/analyzer/compound-assignment-1.c | 71 + .../gcc.dg/analyzer/compound-assignment-2.c | 24 + .../gcc.dg/analyzer/compound-assignment-3.c | 25 + gcc/testsuite/gcc.dg/analyzer/data-model-5b.c | 6 +- gcc/testsuite/gcc.dg/analyzer/data-model-5c.c | 7 +- gcc/testsuite/gcc.dg/analyzer/dot-output.c | 1 + gcc/testsuite/gcc.dg/analyzer/malloc-5.c | 12 + gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/cleanup-13.c | 4 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 1 + gcc/testsuite/gcc.dg/lto/pr94271_0.c | 15 + gcc/testsuite/gcc.dg/lto/pr94271_1.c | 17 + gcc/testsuite/gcc.dg/pr84131.c | 29 + gcc/testsuite/gcc.dg/pr92301.c | 2 +- gcc/testsuite/gcc.dg/pr93573-1.c | 12 + gcc/testsuite/gcc.dg/pr93573-2.c | 6 + gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94166.c | 24 + gcc/testsuite/gcc.dg/pr94167.c | 33 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/pr94211.c | 12 + gcc/testsuite/gcc.dg/pr94269.c | 26 + gcc/testsuite/gcc.dg/pr94277.c | 11 + gcc/testsuite/gcc.dg/pr94283.c | 16 + gcc/testsuite/gcc.dg/pr94286.c | 11 + gcc/testsuite/gcc.dg/pr94291.c | 14 + gcc/testsuite/gcc.dg/pr94292.c | 13 + gcc/testsuite/gcc.dg/pr94344.c | 53 + gcc/testsuite/gcc.dg/pr94368.c | 25 + gcc/testsuite/gcc.dg/pr94436.c | 13 + gcc/testsuite/gcc.dg/pr94526.c | 21 + gcc/testsuite/gcc.dg/sms-compare-debug-1.c | 36 + gcc/testsuite/gcc.dg/sms-compare-debug-2.c | 24 + gcc/testsuite/gcc.dg/tls/pr78796.c | 2 +- gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + gcc/testsuite/gcc.dg/torture/pr94392.c | 22 + gcc/testsuite/gcc.dg/torture/pr94479.c | 12 + gcc/testsuite/gcc.dg/torture/pr94482.c | 36 + gcc/testsuite/gcc.dg/torture/pr94516.c | 31 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.dg/tree-ssa/pr94482-2.c | 50 + gcc/testsuite/gcc.dg/ubsan/pr94423.c | 17 + gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 5 +- gcc/testsuite/gcc.dg/vect/pr93069.c | 10 + gcc/testsuite/gcc.dg/vect/pr94443.c | 13 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 5 +- gcc/testsuite/gcc.target/aarch64/options_set_11.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_12.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_13.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_14.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_15.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_16.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_17.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_18.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_19.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_20.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_21.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_22.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_23.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_24.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_25.c | 11 + gcc/testsuite/gcc.target/aarch64/options_set_26.c | 11 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 + gcc/testsuite/gcc.target/aarch64/pr94398.c | 24 + gcc/testsuite/gcc.target/aarch64/pr94435.c | 25 + gcc/testsuite/gcc.target/aarch64/pr94530.c | 9 + .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- .../aarch64/sve/acle/general/attributes_1.c | 205 + .../aarch64/sve/acle/general/attributes_2.c | 3 + .../aarch64/sve/acle/general/attributes_3.c | 3 + .../aarch64/sve/acle/general/attributes_4.c | 3 + .../aarch64/sve/acle/general/attributes_5.c | 7 + .../aarch64/sve/acle/general/attributes_6.c | 97 + .../aarch64/sve/acle/general/attributes_7.c | 181 + .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 8 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1_1024.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1_128.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1_2048.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1_256.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_1_512.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_2.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_3.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4_1024.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4_128.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4_2048.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4_256.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_4_512.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5_1024.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5_128.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5_2048.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5_256.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_5_512.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6_1024.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6_128.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6_2048.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6_256.c | 2 +- .../gcc.target/aarch64/sve/pcs/return_6_512.c | 2 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 306 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 306 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 306 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 306 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/saves_3.c | 2 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 80 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 80 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_128.c | 2 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- gcc/testsuite/gcc.target/aarch64/sve/pcs/struct.h | 77 + .../gcc.target/aarch64/sve/pcs/struct_1_1024.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_1_128.c | 405 + .../gcc.target/aarch64/sve/pcs/struct_1_2048.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_1_256.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_1_512.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_2_1024.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_2_128.c | 701 + .../gcc.target/aarch64/sve/pcs/struct_2_2048.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_2_256.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_2_512.c | 4 + .../gcc.target/aarch64/sve/pcs/struct_3_128.c | 1092 + .../gcc.target/aarch64/sve/pcs/struct_3_256.c | 1231 + .../gcc.target/aarch64/sve/pcs/struct_3_512.c | 1197 + .../gcc.target/aarch64/sve/pcs/varargs_1.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_f16.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_f32.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_f64.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_s16.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_s32.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_s64.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_s8.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_u16.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_u32.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_u64.c | 2 +- .../gcc.target/aarch64/sve/pcs/varargs_2_u8.c | 2 +- gcc/testsuite/gcc.target/arm/acle/cde-errors.c | 111 + .../gcc.target/arm/acle/cde-mve-error-1.c | 62 + .../gcc.target/arm/acle/cde-mve-error-2.c | 187 + .../gcc.target/arm/acle/cde-mve-error-3.c | 114 + .../gcc.target/arm/acle/cde-mve-full-assembly.c | 1151 + gcc/testsuite/gcc.target/arm/acle/cde-mve-tests.c | 1283 + gcc/testsuite/gcc.target/arm/acle/cde.c | 229 + gcc/testsuite/gcc.target/arm/acle/cde_v_1.c | 94 + gcc/testsuite/gcc.target/arm/acle/cde_v_1_err.c | 127 + gcc/testsuite/gcc.target/arm/acle/cde_v_1_mve.c | 56 + gcc/testsuite/gcc.target/arm/cmp-2.c | 4 +- gcc/testsuite/gcc.target/arm/cmp-3.c | 49 + gcc/testsuite/gcc.target/arm/cmse/cmse-15.c | 152 +- gcc/testsuite/gcc.target/arm/div64-unwinding.c | 1 + gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c | 3 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c | 13 + gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c | 13 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 13 + .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 12 + .../arm/mve/intrinsics/mve_immediates_1_n.c | 62 + .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 67 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 67 + .../arm/mve/intrinsics/mve_load_from_array.c | 19 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 17 + .../mve/intrinsics/mve_vec_extracts_from_memory.c | 40 + .../arm/mve/intrinsics/mve_vector_float.c | 19 + .../arm/mve/intrinsics/mve_vector_float1.c | 23 + .../arm/mve/intrinsics/mve_vector_float2.c | 27 + .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 49 + .../arm/mve/intrinsics/mve_vector_int1.c | 39 + .../arm/mve/intrinsics/mve_vector_int2.c | 33 + .../arm/mve/intrinsics/mve_vector_uint.c | 49 + .../arm/mve/intrinsics/mve_vector_uint1.c | 54 + .../arm/mve/intrinsics/mve_vector_uint2.c | 49 + .../gcc.target/arm/mve/intrinsics/sqrshr.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../gcc.target/arm/mve/intrinsics/sqshl.c | 13 + .../gcc.target/arm/mve/intrinsics/sqshll.c | 13 + .../gcc.target/arm/mve/intrinsics/srshr.c | 13 + .../gcc.target/arm/mve/intrinsics/srshrl.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshl.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../gcc.target/arm/mve/intrinsics/uqshl.c | 13 + .../gcc.target/arm/mve/intrinsics/uqshll.c | 13 + .../gcc.target/arm/mve/intrinsics/urshr.c | 13 + .../gcc.target/arm/mve/intrinsics/urshrl.c | 13 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 21 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 21 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 21 + .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vctp16q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp32q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp64q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp8q.c | 21 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 13 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 22 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 22 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 13 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 13 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 21 + .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 21 + .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 21 + .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 21 + .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 13 + .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 13 + .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 13 + .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 13 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 13 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 22 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 22 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 25 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 25 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 14 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 23 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 21 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 23 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 23 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 23 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 25 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 25 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 21 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 24 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 15 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 15 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 15 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 15 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 21 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 21 + .../vldrdq_gather_shifted_offset_z_s64.c | 21 + .../vldrdq_gather_shifted_offset_z_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 13 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 21 + .../vldrhq_gather_shifted_offset_z_f16.c | 21 + .../vldrhq_gather_shifted_offset_z_s16.c | 21 + .../vldrhq_gather_shifted_offset_z_s32.c | 21 + .../vldrhq_gather_shifted_offset_z_u16.c | 21 + .../vldrhq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 15 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 15 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 15 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 17 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 17 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 17 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 21 + .../vldrwq_gather_shifted_offset_z_f32.c | 21 + .../vldrwq_gather_shifted_offset_z_s32.c | 21 + .../vldrwq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 21 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 21 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 21 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_s16.c | 21 + .../arm/mve/intrinsics/vmulltq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 21 + .../arm/mve/intrinsics/vmulltq_int_u16.c | 21 + .../arm/mve/intrinsics/vmulltq_int_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 21 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_p16.c | 21 + .../arm/mve/intrinsics/vmulltq_poly_p8.c | 21 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpnot.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 21 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 21 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 21 + .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 21 + .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 21 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 21 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 23 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 23 + .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 21 + .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 21 + .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 22 + .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 21 + .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 22 + .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 21 + .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 21 + .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 21 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 23 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 21 + .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 23 + .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 23 + .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 21 + .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 21 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 21 + .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 21 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 21 + .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 21 + .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 21 + .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vqshruntq_n_s16.c | 21 + .../arm/mve/intrinsics/vqshruntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 21 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 44 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 44 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 21 + .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 21 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 21 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 15 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 21 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 15 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 15 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 37 + .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 37 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 21 + .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 21 + .../vstrdq_scatter_shifted_offset_p_s64.c | 21 + .../vstrdq_scatter_shifted_offset_p_u64.c | 21 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 21 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 21 + .../vstrhq_scatter_shifted_offset_p_f16.c | 21 + .../vstrhq_scatter_shifted_offset_p_s16.c | 21 + .../vstrhq_scatter_shifted_offset_p_s32.c | 21 + .../vstrhq_scatter_shifted_offset_p_u16.c | 21 + .../vstrhq_scatter_shifted_offset_p_u32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 21 + .../vstrwq_scatter_shifted_offset_p_f32.c | 21 + .../vstrwq_scatter_shifted_offset_p_s32.c | 21 + .../vstrwq_scatter_shifted_offset_p_u32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 15 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 28 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + gcc/testsuite/gcc.target/arm/mve/mve.exp | 49 + gcc/testsuite/gcc.target/arm/polytypes.c | 2 +- gcc/testsuite/gcc.target/arm/pragma_cde.c | 98 + gcc/testsuite/gcc.target/arm/vfp-1.c | 4 +- gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c | 4 +- gcc/testsuite/gcc.target/arm/vfp-ldmiad.c | 4 +- gcc/testsuite/gcc.target/arm/vfp-stmdbd.c | 4 +- gcc/testsuite/gcc.target/arm/vfp-stmiad.c | 4 +- gcc/testsuite/gcc.target/arm/vnmul-1.c | 4 +- gcc/testsuite/gcc.target/arm/vnmul-3.c | 4 +- gcc/testsuite/gcc.target/arm/vnmul-4.c | 4 +- gcc/testsuite/gcc.target/i386/avx2-pr94460.c | 31 + gcc/testsuite/gcc.target/i386/avx512bw-pr94438.c | 13 + gcc/testsuite/gcc.target/i386/avx512bw-pr94500.c | 28 + gcc/testsuite/gcc.target/i386/avx512bw-pr94509-1.c | 30 + gcc/testsuite/gcc.target/i386/avx512bw-pr94509-2.c | 38 + gcc/testsuite/gcc.target/i386/avx512f-pr94300.c | 21 + gcc/testsuite/gcc.target/i386/avx512f-pr94343.c | 12 + gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c | 12 + gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c | 12 + gcc/testsuite/gcc.target/i386/avx512vlbw-pr94438.c | 13 + gcc/testsuite/gcc.target/i386/pr57193.c | 3 +- gcc/testsuite/gcc.target/i386/pr81213-2.c | 12 + gcc/testsuite/gcc.target/i386/pr81213.c | 12 +- gcc/testsuite/gcc.target/i386/pr89229-7a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-7b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7c.c | 7 + gcc/testsuite/gcc.target/i386/pr94283.c | 5 + gcc/testsuite/gcc.target/i386/pr94308.c | 31 + gcc/testsuite/gcc.target/i386/pr94417-1.c | 20 + gcc/testsuite/gcc.target/i386/pr94417-2.c | 21 + gcc/testsuite/gcc.target/i386/pr94417-3.c | 19 + gcc/testsuite/gcc.target/i386/pr94461.c | 12 + gcc/testsuite/gcc.target/i386/pr94467-1.c | 40 + gcc/testsuite/gcc.target/i386/pr94467-2.c | 48 + .../gcc.target/microblaze/others/builtin-trap.c | 2 +- gcc/testsuite/gcc.target/powerpc/bswap64-4.c | 6 +- gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 47 + gcc/testsuite/gcc.target/powerpc/pragma_power6.c | 17 + gcc/testsuite/gcc.target/powerpc/pragma_power7.c | 32 + gcc/testsuite/gcc.target/powerpc/pragma_power8.c | 52 + gcc/testsuite/gcc.target/powerpc/pragma_power9.c | 63 + .../gcc.target/powerpc/vsu/vec-all-nez-7.c | 3 +- .../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 3 +- gcc/testsuite/gdc.dg/asm1.d | 9 + gcc/testsuite/gdc.dg/asm5.d | 12 + gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/imports/pr92216.d | 22 + gcc/testsuite/gdc.dg/pr90136a.d | 21 + gcc/testsuite/gdc.dg/pr90136b.d | 21 + gcc/testsuite/gdc.dg/pr90136c.d | 9 + gcc/testsuite/gdc.dg/pr92216.d | 13 + gcc/testsuite/gdc.dg/pr92309.d | 25 + gcc/testsuite/gdc.dg/pr93038.d | 10 + gcc/testsuite/gdc.dg/pr93038b.d | 11 + gcc/testsuite/gdc.dg/pr94424.d | 19 + gcc/testsuite/gdc.test/compilable/compilable.exp | 30 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + .../gdc.test/fail_compilation/fail_compilation.exp | 30 + gcc/testsuite/gdc.test/gdc-test.exp | 469 - gcc/testsuite/gdc.test/runnable/runnable.exp | 35 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- .../gdc.test/{runnable => runnable_cxx}/cabi1.d | 0 .../{runnable => runnable_cxx}/cpp_abi_tests.d | 0 .../gdc.test/{runnable => runnable_cxx}/cppa.d | 0 .../{runnable => runnable_cxx}/externmangle.d | 0 .../{runnable => runnable_cxx}/externmangle2.d | 0 .../extra-files/cabi2.cpp | 0 .../extra-files/cpp_abi_tests.cpp | 0 .../extra-files/cppb.cpp | 0 .../extra-files/externmangle.cpp | 0 .../extra-files/externmangle2.cpp | 0 .../gdc.test/runnable_cxx/runnable_cxx.exp | 46 + gcc/testsuite/gfortran.dg/associate_51.f90 | 2 +- gcc/testsuite/gfortran.dg/associate_53.f90 | 71 + gcc/testsuite/gfortran.dg/assumed_rank_19.f90 | 37 + gcc/testsuite/gfortran.dg/asynchronous_5.f03 | 41 + gcc/testsuite/gfortran.dg/bessel_5_redux.f90 | 85 + gcc/testsuite/gfortran.dg/dec_math.f90 | 801 +- gcc/testsuite/gfortran.dg/dec_math_2.f90 | 14 + gcc/testsuite/gfortran.dg/dec_math_3.f90 | 8 + gcc/testsuite/gfortran.dg/dec_math_4.f90 | 8 + gcc/testsuite/gfortran.dg/dec_structure_28.f90 | 35 + gcc/testsuite/gfortran.dg/dtio_35.f90 | 50 + gcc/testsuite/gfortran.dg/f2003_io_8.f03 | 2 +- .../gfortran.dg/graphite/vect-pr94043.f90 | 18 + gcc/testsuite/gfortran.dg/ieee/dec_math_1.f90 | 231 + gcc/testsuite/gfortran.dg/io_constraints_15.f90 | 11 + gcc/testsuite/gfortran.dg/io_constraints_16.f90 | 11 + gcc/testsuite/gfortran.dg/io_constraints_17.f90 | 11 + gcc/testsuite/gfortran.dg/io_constraints_18.f90 | 9 + gcc/testsuite/gfortran.dg/io_constraints_8.f90 | 2 +- gcc/testsuite/gfortran.dg/io_tags_1.f90 | 19 + gcc/testsuite/gfortran.dg/io_tags_10.f90 | 103 + gcc/testsuite/gfortran.dg/io_tags_2.f90 | 30 + gcc/testsuite/gfortran.dg/io_tags_3.f90 | 17 + gcc/testsuite/gfortran.dg/io_tags_4.f90 | 17 + gcc/testsuite/gfortran.dg/io_tags_5.f90 | 17 + gcc/testsuite/gfortran.dg/io_tags_6.f90 | 175 + gcc/testsuite/gfortran.dg/io_tags_7.f90 | 103 + gcc/testsuite/gfortran.dg/io_tags_8.f90 | 18 + gcc/testsuite/gfortran.dg/io_tags_9.f90 | 18 + gcc/testsuite/gfortran.dg/iomsg_2.f90 | 36 +- .../gfortran.dg/iso_c_binding_compiler_1.f90 | 3 + .../gfortran.dg/iso_c_binding_compiler_3.f90 | 3 + gcc/testsuite/gfortran.dg/module_procedure_3.f90 | 27 + gcc/testsuite/gfortran.dg/pr66725.f90 | 42 +- gcc/testsuite/gfortran.dg/pr88205.f90 | 6 +- gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93484_1.f90 | 8 + gcc/testsuite/gfortran.dg/pr93484_2.f90 | 8 + gcc/testsuite/gfortran.dg/pr93498_1.f90 | 11 + gcc/testsuite/gfortran.dg/pr93498_2.f90 | 12 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/gfortran.dg/pr93686_1.f90 | 10 + gcc/testsuite/gfortran.dg/pr93686_2.f90 | 10 + gcc/testsuite/gfortran.dg/pr93686_3.f90 | 9 + gcc/testsuite/gfortran.dg/pr93686_4.f90 | 8 + gcc/testsuite/gfortran.dg/pr94030_1.f90 | 11 + gcc/testsuite/gfortran.dg/pr94030_2.f90 | 33 + gcc/testsuite/gfortran.dg/pr94285.f90 | 5 + gcc/testsuite/gfortran.dg/pr94329.f90 | 12 + gcc/testsuite/gfortran.dg/select_rank_4.f90 | 26 + .../gfortran.dg/unlimited_polymorphic_31.f03 | 3 + gcc/testsuite/gfortran.dg/vect/pr83232.f90 | 6 +- gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 +- gcc/testsuite/gfortran.dg/write_check4.f90 | 4 +- gcc/testsuite/gfortran.dg/write_check5.f90 | 24 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 30 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/jit.dg/test-version.c | 26 + gcc/testsuite/lib/gdc-utils.exp | 475 + gcc/testsuite/lib/gdc.exp | 120 +- gcc/testsuite/lib/scanasm.exp | 18 +- gcc/testsuite/lib/target-supports.exp | 184 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-cfg.c | 3 + gcc/tree-core.h | 3 +- gcc/tree-data-ref.c | 2 +- gcc/tree-if-conv.c | 24 +- gcc/tree-inline.c | 4 +- gcc/tree-iterator.c | 41 + gcc/tree-iterator.h | 1 + gcc/tree-object-size.c | 5 +- gcc/tree-sra.c | 70 +- gcc/tree-ssa-dce.c | 8 +- gcc/tree-ssa-dom.c | 11 +- gcc/tree-ssa-dse.c | 4 +- gcc/tree-ssa-forwprop.c | 66 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-loop-ivopts.c | 18 +- gcc/tree-ssa-loop-manip.c | 12 +- gcc/tree-ssa-loop-niter.c | 2 +- gcc/tree-ssa-loop-split.c | 2 +- gcc/tree-ssa-math-opts.c | 8 +- gcc/tree-ssa-phiopt.c | 10 +- gcc/tree-ssa-propagate.c | 19 +- gcc/tree-ssa-reassoc.c | 23 +- gcc/tree-ssa-sccvn.c | 2 + gcc/tree-ssa-strlen.c | 259 +- gcc/tree-ssa-strlen.h | 2 +- gcc/tree-streamer-in.c | 1 + gcc/tree-streamer-out.c | 1 + gcc/tree-vect-generic.c | 25 +- gcc/tree-vect-loop.c | 52 +- gcc/tree-vect-patterns.c | 4 +- gcc/tree-vect-slp.c | 58 +- gcc/tree-vect-stmts.c | 210 +- gcc/tree.c | 38 +- gcc/tree.def | 2 +- gcc/tree.h | 11 +- gcc/var-tracking.c | 50 +- gcc/varasm.c | 20 + include/ChangeLog | 29 + include/lto-symtab.h | 13 + include/plugin-api.h | 93 +- libatomic/ChangeLog | 10 + libatomic/configure | 3 + libatomic/configure.ac | 1 + libatomic/testsuite/Makefile.am | 2 + libatomic/testsuite/Makefile.in | 5 +- libatomic/testsuite/libatomic-site-extra.exp.in | 1 + libcpp/po/ChangeLog | 8 + libcpp/po/eo.po | 81 +- libcpp/po/sr.po | 78 +- libgcc/ChangeLog | 42 + libgcc/config/arm/lib1funcs.S | 33 +- libgcc/config/arm/t-arm | 3 + libgcc/config/s390/tpf-unwind.h | 132 +- libgcc/generic-morestack.c | 56 + libgfortran/ChangeLog | 9 + libgfortran/Makefile.am | 1 + libgfortran/Makefile.in | 19 +- libgfortran/gfortran.map | 12 + libgfortran/intrinsics/trigd.c | 205 + libgfortran/intrinsics/trigd.inc | 464 + libgfortran/intrinsics/trigd_lib.inc | 147 + libgo/MERGE | 2 +- libgo/VERSION | 2 +- libgo/go/cmd/cgo/gcc.go | 19 +- libgo/go/cmd/go/alldocs.go | 52 +- libgo/go/cmd/go/internal/generate/generate.go | 3 +- libgo/go/cmd/go/internal/modcmd/verify.go | 11 +- libgo/go/cmd/go/internal/modfetch/cache.go | 40 +- libgo/go/cmd/go/internal/modfetch/fetch.go | 61 +- libgo/go/cmd/go/internal/modload/build.go | 4 +- libgo/go/cmd/go/internal/modload/help.go | 52 +- .../go/cmd/go/internal/robustio/robustio_flaky.go | 2 +- libgo/go/cmd/go/internal/test/test.go | 10 +- libgo/go/cmd/go/internal/work/exec.go | 3 + libgo/go/cmd/go/testdata/script/mod_edit_go.txt | 7 + libgo/go/go/build/deps_test.go | 5 +- .../go/internal/syscall/execenv/execenv_default.go | 19 + .../go/internal/syscall/execenv/execenv_windows.go | 54 + libgo/go/os/env_default.go | 13 - libgo/go/os/env_windows.go | 44 - libgo/go/os/exec/exec.go | 15 +- libgo/go/os/exec_posix.go | 3 +- libgo/go/runtime/alg.go | 12 +- libgo/go/runtime/checkptr.go | 4 +- libgo/go/runtime/checkptr_test.go | 9 +- libgo/go/runtime/defer_test.go | 120 + libgo/go/runtime/export_test.go | 25 + libgo/go/runtime/hash_test.go | 49 + libgo/go/runtime/mbitmap.go | 6 +- libgo/go/runtime/mgc.go | 48 +- libgo/go/runtime/mkpreempt.go | 43 +- libgo/go/runtime/panic.go | 15 +- libgo/go/runtime/pprof/map.go | 3 +- libgo/go/runtime/pprof/pprof_test.go | 59 +- libgo/go/runtime/pprof/proto.go | 45 +- libgo/go/runtime/pprof/proto_test.go | 13 + libgo/go/runtime/pprof/runtime.go | 3 + libgo/go/runtime/runtime2.go | 4 + libgo/go/runtime/signal_unix.go | 1 + libgo/go/runtime/stubs.go | 7 + libgo/go/runtime/symtab.go | 31 + libgo/go/runtime/testdata/testprog/checkptr.go | 11 +- libgo/go/runtime/time.go | 256 +- libgo/go/testing/testing.go | 11 +- libgo/go/time/time_test.go | 40 +- libgo/libgo-packages.txt | 1 + libgo/misc/cgo/testgodefs/testdata/issue37479.go | 33 + libgo/misc/cgo/testgodefs/testdata/issue37621.go | 23 + libgo/misc/cgo/testgodefs/testdata/main.go | 8 + libgo/misc/cgo/testgodefs/testgodefs_test.go | 2 + libgo/runtime/go-callers.c | 36 + libgomp/ChangeLog | 105 + libgomp/configure | 3 + libgomp/configure.ac | 1 + libgomp/target.c | 18 +- libgomp/testsuite/Makefile.am | 2 + libgomp/testsuite/Makefile.in | 6 +- libgomp/testsuite/libgomp-site-extra.exp.in | 1 + libgomp/testsuite/libgomp-test-support.exp.in | 2 - libgomp/testsuite/libgomp.c++/pr93931.C | 120 + .../libgomp.c-c++-common/function-not-offloaded.c | 1 + libgomp/testsuite/libgomp.c/target-link-1.c | 3 - .../libgomp.fortran/target-enter-data-1.f90 | 38 + .../testsuite/libgomp.oacc-c++/declare-pr94120.C | 57 + .../libgomp.oacc-c++/firstprivate-mappings-1.C | 9 + .../firstprivate-mappings-1.c | 9 + .../libgomp.oacc-c-c++-common/pr85381-2.c | 20 +- .../libgomp.oacc-c-c++-common/pr85381-4.c | 5 +- .../static-dynamic-lifetimes-1-lib.c | 3 + .../static-dynamic-lifetimes-1.c | 160 + .../static-dynamic-lifetimes-2-lib.c | 3 + .../static-dynamic-lifetimes-2.c | 166 + .../static-dynamic-lifetimes-3-lib.c | 3 + .../static-dynamic-lifetimes-3.c | 183 + .../static-dynamic-lifetimes-4-lib.c | 3 + .../static-dynamic-lifetimes-4.c | 64 + .../static-dynamic-lifetimes-5-lib.c | 3 + .../static-dynamic-lifetimes-5.c | 56 + .../static-dynamic-lifetimes-6-lib.c | 3 + .../static-dynamic-lifetimes-6.c | 42 + .../static-dynamic-lifetimes-7-lib.c | 3 + .../static-dynamic-lifetimes-7.c | 42 + .../static-dynamic-lifetimes-8-lib.c | 3 + .../static-dynamic-lifetimes-8.c | 47 + .../libgomp.oacc-fortran/atomic_capture-1.f90 | 30 +- libphobos/ChangeLog | 94 + libphobos/Makefile.in | 4 +- libphobos/configure | 232 +- libphobos/configure.ac | 37 +- libphobos/d_rules.am | 11 - libphobos/libdruntime/MERGE | 2 +- libphobos/libdruntime/Makefile.am | 46 +- libphobos/libdruntime/Makefile.in | 339 +- libphobos/libdruntime/config/s390/get_tls_offset.S | 25 + .../libdruntime/config/systemz/get_tls_offset.S | 79 + libphobos/libdruntime/core/cpuid.d | 36 +- libphobos/libdruntime/core/sys/posix/signal.d | 47 +- libphobos/libdruntime/gcc/sections/elf_shared.d | 10 +- libphobos/libdruntime/gcstub/gc.d | 388 - libphobos/m4/druntime.m4 | 16 - libphobos/m4/druntime/cpu.m4 | 10 + libphobos/m4/druntime/libraries.m4 | 26 - libphobos/m4/druntime/os.m4 | 31 +- libphobos/src/MERGE | 2 +- libphobos/src/Makefile.am | 17 +- libphobos/src/Makefile.in | 35 +- libphobos/src/std/algorithm/iteration.d | 2 +- libphobos/src/std/math.d | 312 +- libphobos/testsuite/Makefile.in | 2 + libphobos/testsuite/lib/libphobos.exp | 4 - libphobos/testsuite/testsuite_flags.in | 3 +- libstdc++-v3/ChangeLog | 331 + .../doc/html/manual/appendix_contributing.html | 2 +- libstdc++-v3/doc/html/manual/appendix_free.html | 2 +- .../doc/xml/manual/appendix_contributing.xml | 2 +- libstdc++-v3/doc/xml/manual/appendix_free.xml | 2 +- libstdc++-v3/include/bits/char_traits.h | 101 +- libstdc++-v3/include/bits/fs_fwd.h | 42 - libstdc++-v3/include/bits/fs_path.h | 11 +- libstdc++-v3/include/bits/iterator_concepts.h | 50 + libstdc++-v3/include/bits/ptr_traits.h | 11 +- libstdc++-v3/include/bits/range_access.h | 27 +- libstdc++-v3/include/bits/range_cmp.h | 3 + libstdc++-v3/include/bits/slice_array.h | 5 + libstdc++-v3/include/bits/stl_algobase.h | 2 +- libstdc++-v3/include/bits/stl_iterator.h | 276 +- .../include/bits/stl_iterator_base_types.h | 4 +- libstdc++-v3/include/bits/stream_iterator.h | 4 +- libstdc++-v3/include/bits/streambuf_iterator.h | 4 +- libstdc++-v3/include/bits/unique_ptr.h | 25 + libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- libstdc++-v3/include/experimental/executor | 235 +- libstdc++-v3/include/experimental/socket | 18 +- libstdc++-v3/include/std/charconv | 25 +- libstdc++-v3/include/std/chrono | 206 +- libstdc++-v3/include/std/complex | 2 + libstdc++-v3/include/std/concepts | 2 +- libstdc++-v3/include/std/condition_variable | 3 + libstdc++-v3/include/std/future | 3 + libstdc++-v3/include/std/mutex | 3 + libstdc++-v3/include/std/shared_mutex | 6 + libstdc++-v3/include/std/stop_token | 12 + libstdc++-v3/include/std/string_view | 1 + libstdc++-v3/include/std/thread | 3 + libstdc++-v3/include/std/type_traits | 80 +- libstdc++-v3/include/std/version | 7 +- libstdc++-v3/libsupc++/compare | 49 +- .../comparisons/algorithms/partial_order.cc | 4 + .../comparisons/algorithms/strong_order.cc | 4 + .../comparisons/algorithms/weak_order.cc | 4 + .../allocator_traits/members/92878_92947.cc | 51 + .../testsuite/20_util/any/assign/92878_92947.cc | 46 + .../testsuite/20_util/any/cons/92878_92947.cc | 46 + libstdc++-v3/testsuite/20_util/bind/91371.cc | 2 +- .../testsuite/20_util/default_delete/48631_neg.cc | 2 +- .../testsuite/20_util/default_delete/void_neg.cc | 2 +- libstdc++-v3/testsuite/20_util/from_chars/1.cc | 16 +- libstdc++-v3/testsuite/20_util/from_chars/2.cc | 130 +- .../testsuite/20_util/from_chars/compare.cc | 50 + .../20_util/is_constructible/92878_92947.cc | 49 + .../testsuite/20_util/is_constructible/value-2.cc | 4 + .../testsuite/20_util/is_function/91371.cc | 2 +- .../20_util/is_member_function_pointer/91371.cc | 2 +- .../20_util/is_nothrow_constructible/94003.cc | 46 + libstdc++-v3/testsuite/20_util/is_object/91371.cc | 2 +- .../20_util/optional/assignment/92878_92947.cc | 47 + .../testsuite/20_util/optional/cons/92878_92947.cc | 46 + .../testsuite/20_util/pair/cons/92878_92947.cc | 49 + .../20_util/shared_ptr/creation/92878_92947.cc | 46 + .../construct_at/92878_92947.cc | 50 + .../testsuite/20_util/time_point/cons/81468.cc | 8 +- .../time_point/requirements/duration_neg.cc | 32 + libstdc++-v3/testsuite/20_util/to_address/1_neg.cc | 2 +- libstdc++-v3/testsuite/20_util/to_address/debug.cc | 36 + libstdc++-v3/testsuite/20_util/to_chars/1.cc | 30 +- libstdc++-v3/testsuite/20_util/to_chars/2.cc | 4 +- libstdc++-v3/testsuite/20_util/to_chars/compare.cc | 51 + .../20_util/unique_ptr/comparison/compare.cc | 88 + .../20_util/unique_ptr/comparison/compare_c++20.cc | 98 + .../20_util/unique_ptr/creation/92878_92947.cc | 46 + .../20_util/uses_allocator/92878_92947.cc | 67 + .../testsuite/20_util/variant/92878_92947.cc | 91 + .../operations/copy/char/constexpr.cc | 32 + .../operations/copy/wchar_t/constexpr.cc | 32 + .../deque/modifiers/emplace/92878_92947.cc | 62 + .../forward_list/modifiers/92878_92947.cc | 62 + .../list/modifiers/emplace/92878_92947.cc | 78 + .../map/modifiers/emplace/92878_92947.cc | 137 + .../multimap/modifiers/emplace/92878_92947.cc | 71 + .../multiset/modifiers/emplace/92878_92947.cc | 70 + .../23_containers/priority_queue/92878_92947.cc | 52 + .../testsuite/23_containers/queue/92878_92947.cc | 47 + .../set/modifiers/emplace/92878_92947.cc | 70 + .../testsuite/23_containers/stack/92878_92947.cc | 47 + .../unordered_map/modifiers/92878_92947.cc | 137 + .../unordered_multimap/modifiers/92878_92947.cc | 71 + .../unordered_multiset/modifiers/92878_92947.cc | 78 + .../unordered_set/modifiers/92878_92947.cc | 78 + .../vector/modifiers/emplace/92878_92947.cc | 61 + .../24_iterators/back_insert_iterator/constexpr.cc | 54 + .../front_insert_iterator/constexpr.cc | 54 + .../headers/iterator/synopsis_c++17.cc | 18 + .../24_iterators/insert_iterator/constexpr.cc | 57 + .../24_iterators/move_iterator/greedy_ops.cc | 8 +- .../24_iterators/move_iterator/input_iterator.cc | 42 + .../24_iterators/move_iterator/move_only.cc | 61 + .../24_iterators/move_iterator/rel_ops_c++20.cc | 163 + .../24_iterators/reverse_iterator/greedy_ops.cc | 8 +- .../24_iterators/reverse_iterator/rel_ops_c++20.cc | 193 + .../testsuite/26_numerics/slice/compare.cc | 48 + .../27_io/filesystem/path/generic/94242.cc | 52 + .../filesystem/path/generic/generic_string.cc | 32 + .../30_threads/condition_variable/members/2.cc | 2 + .../condition_variable/members/clock_neg.cc | 61 + .../condition_variable_any/members/clock_neg.cc | 61 + .../30_threads/future/members/clock_neg.cc | 59 + .../recursive_timed_mutex/try_lock_until/3.cc | 2 +- .../try_lock_until/clock_neg.cc | 57 + .../30_threads/shared_future/members/clock_neg.cc | 59 + .../30_threads/shared_lock/locking/clock_neg.cc | 59 + .../shared_timed_mutex/try_lock_until/1.cc | 87 + .../shared_timed_mutex/try_lock_until/2.cc | 74 + .../shared_timed_mutex/try_lock_until/clock_neg.cc | 57 + .../30_threads/timed_mutex/try_lock_until/3.cc | 2 +- .../30_threads/timed_mutex/try_lock_until/4.cc | 2 +- .../timed_mutex/try_lock_until/clock_neg.cc | 57 + .../30_threads/unique_lock/locking/clock_neg.cc | 59 + .../filesystem/path/generic/generic_string.cc | 46 +- .../net/execution_context/make_service.cc | 36 + .../net/execution_context/use_service.cc | 6 +- .../testsuite/experimental/net/executor/1.cc | 93 + .../std/ranges/headers/ranges/synopsis.cc | 6 + .../testsuite/std/time/clock/file/members.cc | 39 + .../testsuite/std/time/clock/file/overview.cc | 43 + libstdc++-v3/testsuite/std/time/syn_c++20.cc | 199 + libstdc++-v3/testsuite/std/time/traits/is_clock.cc | 141 + libstdc++-v3/testsuite/util/slow_clock.h | 3 + lto-plugin/ChangeLog | 20 + lto-plugin/lto-plugin.c | 141 +- 3515 files changed, 350798 insertions(+), 150306 deletions(-) create mode 100644 gcc/config/arm/arm-builtins.h create mode 100644 gcc/config/arm/arm_cde.h create mode 100644 gcc/config/arm/arm_cde_builtins.def create mode 100644 gcc/config/arm/arm_mve.h create mode 100644 gcc/config/arm/arm_mve_builtins.def create mode 100644 gcc/config/arm/arm_mve_types.h create mode 100644 gcc/config/arm/mve.md create mode 100644 gcc/fortran/trigd_fe.inc create mode 100644 gcc/testsuite/c-c++-common/attr-copy.c create mode 100644 gcc/testsuite/c-c++-common/goacc-gomp/pr93465-1.c create mode 100644 gcc/testsuite/c-c++-common/goacc/declare-pr94120.c create mode 100644 gcc/testsuite/c-c++-common/pr94385.c create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle75.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic5.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic7.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic8.C create mode 100644 gcc/testsuite/g++.dg/concepts/pr94252.C create mode 100644 gcc/testsuite/g++.dg/conversion/op7.C create mode 100644 gcc/testsuite/g++.dg/coroutines/co-await-syntax-10.C create mode 100644 gcc/testsuite/g++.dg/coroutines/co-await-syntax-11.C create mode 100644 gcc/testsuite/g++.dg/coroutines/pr94528.C rename gcc/testsuite/g++.dg/coroutines/torture/{co-await-14-template-traits.C => c [...] rename gcc/testsuite/g++.dg/coroutines/torture/{co-await-15-capture-comp-ref.C => [...] create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/exceptions-test-01-n4849-a.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/symmetric-transfer-00-basic.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-constexpr1.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept57.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic-alias2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl1.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi4.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi5.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-static1.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr79937-5.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr90996.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/lambda-this4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/lambda-this5.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/lambda-this6.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/pr81349.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-nonbool1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-nonbool2.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-placeholder2.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-pmf1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-requires21.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/lambda-generic7.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/lambda-uneval11.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/paren-init22.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/paren-init23.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/paren-init24.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/paren-init25.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/spaceship-eq9.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/spaceship-err4.C create mode 100644 gcc/testsuite/g++.dg/debug/pr94272.C create mode 100644 gcc/testsuite/g++.dg/debug/pr94273.C create mode 100644 gcc/testsuite/g++.dg/debug/pr94281.C create mode 100644 gcc/testsuite/g++.dg/debug/pr94323.C create mode 100644 gcc/testsuite/g++.dg/debug/pr94459.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-access-2.C create mode 100644 gcc/testsuite/g++.dg/ext/is_constructible5.C create mode 100644 gcc/testsuite/g++.dg/ext/pr94197.C create mode 100644 gcc/testsuite/g++.dg/goacc/declare-pr94120.C create mode 100644 gcc/testsuite/g++.dg/gomp/pr94477.C create mode 100644 gcc/testsuite/g++.dg/gomp/pr94512.C create mode 100644 gcc/testsuite/g++.dg/init/aggr14.C create mode 100644 gcc/testsuite/g++.dg/lookup/pr84733.C create mode 100644 gcc/testsuite/g++.dg/lookup/pr94257.C create mode 100644 gcc/testsuite/g++.dg/opt/pr94223.C create mode 100644 gcc/testsuite/g++.dg/opt/pr94441.C create mode 100644 gcc/testsuite/g++.dg/opt/pr94468.C create mode 100644 gcc/testsuite/g++.dg/other/pr94326.C create mode 100644 gcc/testsuite/g++.dg/other/pr94339.C create mode 100644 gcc/testsuite/g++.dg/pr93674.C create mode 100644 gcc/testsuite/g++.dg/pr94314-2.C create mode 100644 gcc/testsuite/g++.dg/pr94314-3.C create mode 100644 gcc/testsuite/g++.dg/pr94314.C create mode 100644 gcc/testsuite/g++.dg/template/array33.C create mode 100644 gcc/testsuite/g++.dg/template/array34.C create mode 100644 gcc/testsuite/g++.dg/template/defarg22.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name10.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name11.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name12.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name13.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name14.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name7.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name8.C create mode 100644 gcc/testsuite/g++.dg/template/dependent-name9.C create mode 100644 gcc/testsuite/g++.dg/template/dr1710-2.C create mode 100644 gcc/testsuite/g++.dg/template/dr1710.C create mode 100644 gcc/testsuite/g++.dg/template/dr1794.C create mode 100644 gcc/testsuite/g++.dg/template/dr314.C create mode 100644 gcc/testsuite/g++.dg/template/koenig11.C create mode 100644 gcc/testsuite/g++.dg/template/template-keyword2.C create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94303.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr93940.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94403.C create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/ubsan/vptr-15.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wduplicated-cond1.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-tags-3.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-tags-4.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-tags-5.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-tags-6.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-6.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-7.C create mode 100644 gcc/testsuite/g++.target/aarch64/pr94052.C create mode 100644 gcc/testsuite/g++.target/arm/cde_mve.C create mode 100644 gcc/testsuite/g++.target/arm/mve.exp create mode 100644 gcc/testsuite/g++.target/i386/pr94185.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94144.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94179.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94238.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94488.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94412.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94524-1.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94524-2.c create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/Walloca-larger-than-3.c create mode 100644 gcc/testsuite/gcc.dg/Walloca-larger-than-3.h create mode 100644 gcc/testsuite/gcc.dg/Wvla-larger-than-4.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-1.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-2.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-3.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/malloc-5.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94271_0.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94271_1.c create mode 100644 gcc/testsuite/gcc.dg/pr84131.c create mode 100644 gcc/testsuite/gcc.dg/pr93573-1.c create mode 100644 gcc/testsuite/gcc.dg/pr93573-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94015.c create mode 100644 gcc/testsuite/gcc.dg/pr94166.c create mode 100644 gcc/testsuite/gcc.dg/pr94167.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.dg/pr94269.c create mode 100644 gcc/testsuite/gcc.dg/pr94277.c create mode 100644 gcc/testsuite/gcc.dg/pr94283.c create mode 100644 gcc/testsuite/gcc.dg/pr94286.c create mode 100644 gcc/testsuite/gcc.dg/pr94291.c create mode 100644 gcc/testsuite/gcc.dg/pr94292.c create mode 100644 gcc/testsuite/gcc.dg/pr94344.c create mode 100644 gcc/testsuite/gcc.dg/pr94368.c create mode 100644 gcc/testsuite/gcc.dg/pr94436.c create mode 100644 gcc/testsuite/gcc.dg/pr94526.c create mode 100644 gcc/testsuite/gcc.dg/sms-compare-debug-1.c create mode 100644 gcc/testsuite/gcc.dg/sms-compare-debug-2.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94392.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94479.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94482.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94516.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93435.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr94482-2.c create mode 100644 gcc/testsuite/gcc.dg/ubsan/pr94423.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr93069.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr94443.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_11.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_12.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_13.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_14.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_15.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_17.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_18.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_19.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_20.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_21.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_22.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_23.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_24.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_25.c create mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_26.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94201.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94398.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94435.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94530.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/attributes_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct.h create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_1_1024.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_1_128.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_1_2048.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_1_256.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_1_512.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_2_1024.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_2_128.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_2_2048.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_2_256.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_2_512.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_128.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_256.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pcs/struct_3_512.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-errors.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-mve-error-1.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-mve-error-3.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde-mve-tests.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde_v_1.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde_v_1_err.c create mode 100644 gcc/testsuite/gcc.target/arm/acle/cde_v_1_mve.c create mode 100644 gcc/testsuite/gcc.target/arm/cmp-3.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_load_from_array.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vec_extracts_fr [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve.exp create mode 100644 gcc/testsuite/gcc.target/arm/pragma_cde.c create mode 100644 gcc/testsuite/gcc.target/i386/avx2-pr94460.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr94438.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr94500.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr94509-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr94509-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr94300.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr94343.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vlbw-pr94438.c create mode 100644 gcc/testsuite/gcc.target/i386/pr81213-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94283.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94308.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94417-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94417-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94417-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94461.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94467-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94467-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pragma_misc9.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pragma_power6.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pragma_power7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pragma_power8.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pragma_power9.c create mode 100644 gcc/testsuite/gdc.dg/asm5.d create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/imports/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr90136a.d create mode 100644 gcc/testsuite/gdc.dg/pr90136b.d create mode 100644 gcc/testsuite/gdc.dg/pr90136c.d create mode 100644 gcc/testsuite/gdc.dg/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92309.d create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gdc.dg/pr94424.d create mode 100644 gcc/testsuite/gdc.test/compilable/compilable.exp create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail_compilation.exp delete mode 100644 gcc/testsuite/gdc.test/gdc-test.exp create mode 100644 gcc/testsuite/gdc.test/runnable/runnable.exp rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/cabi1.d (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/cpp_abi_tests.d (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/cppa.d (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/externmangle.d (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/externmangle2.d (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/extra-files/cabi2.cpp (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/extra-files/cpp_abi_tests [...] rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/extra-files/cppb.cpp (100%) rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/extra-files/externmangle. [...] rename gcc/testsuite/gdc.test/{runnable => runnable_cxx}/extra-files/externmangle2 [...] create mode 100644 gcc/testsuite/gdc.test/runnable_cxx/runnable_cxx.exp create mode 100644 gcc/testsuite/gfortran.dg/associate_53.f90 create mode 100644 gcc/testsuite/gfortran.dg/assumed_rank_19.f90 create mode 100644 gcc/testsuite/gfortran.dg/asynchronous_5.f03 create mode 100644 gcc/testsuite/gfortran.dg/bessel_5_redux.f90 create mode 100644 gcc/testsuite/gfortran.dg/dec_math_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/dec_math_3.f90 create mode 100644 gcc/testsuite/gfortran.dg/dec_math_4.f90 create mode 100644 gcc/testsuite/gfortran.dg/dec_structure_28.f90 create mode 100644 gcc/testsuite/gfortran.dg/dtio_35.f90 create mode 100644 gcc/testsuite/gfortran.dg/graphite/vect-pr94043.f90 create mode 100644 gcc/testsuite/gfortran.dg/ieee/dec_math_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_constraints_15.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_constraints_16.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_constraints_17.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_constraints_18.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_10.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_3.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_4.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_5.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_6.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_7.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_8.f90 create mode 100644 gcc/testsuite/gfortran.dg/io_tags_9.f90 create mode 100644 gcc/testsuite/gfortran.dg/module_procedure_3.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93484_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93484_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93498_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93498_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93686_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93686_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93686_3.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93686_4.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94030_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94030_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94285.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94329.f90 create mode 100644 gcc/testsuite/gfortran.dg/select_rank_4.f90 create mode 100644 gcc/testsuite/gfortran.dg/write_check5.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c create mode 100644 gcc/testsuite/jit.dg/test-version.c create mode 100644 gcc/testsuite/lib/gdc-utils.exp create mode 100644 libatomic/testsuite/libatomic-site-extra.exp.in create mode 100644 libgfortran/intrinsics/trigd.c create mode 100644 libgfortran/intrinsics/trigd.inc create mode 100644 libgfortran/intrinsics/trigd_lib.inc create mode 100644 libgo/go/internal/syscall/execenv/execenv_default.go create mode 100644 libgo/go/internal/syscall/execenv/execenv_windows.go delete mode 100644 libgo/go/os/env_default.go delete mode 100644 libgo/go/os/env_windows.go create mode 100644 libgo/misc/cgo/testgodefs/testdata/issue37479.go create mode 100644 libgo/misc/cgo/testgodefs/testdata/issue37621.go create mode 100644 libgomp/testsuite/libgomp-site-extra.exp.in create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C create mode 100644 libgomp/testsuite/libgomp.fortran/target-enter-data-1.f90 create mode 100644 libgomp/testsuite/libgomp.oacc-c++/declare-pr94120.C create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libgomp/testsuite/libgomp.oacc-c-c++-common/static-dynamic-life [...] create mode 100644 libphobos/libdruntime/config/s390/get_tls_offset.S create mode 100644 libphobos/libdruntime/config/systemz/get_tls_offset.S delete mode 100644 libphobos/libdruntime/gcstub/gc.d create mode 100644 libstdc++-v3/testsuite/20_util/allocator_traits/members/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/any/assign/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/any/cons/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/from_chars/compare.cc create mode 100644 libstdc++-v3/testsuite/20_util/is_constructible/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc create mode 100644 libstdc++-v3/testsuite/20_util/optional/assignment/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/optional/cons/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/pair/cons/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/shared_ptr/creation/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/specialized_algorithms/construct [...] create mode 100644 libstdc++-v3/testsuite/20_util/time_point/requirements/duration_neg.cc create mode 100644 libstdc++-v3/testsuite/20_util/to_address/debug.cc create mode 100644 libstdc++-v3/testsuite/20_util/to_chars/compare.cc create mode 100644 libstdc++-v3/testsuite/20_util/unique_ptr/comparison/compare.cc create mode 100644 libstdc++-v3/testsuite/20_util/unique_ptr/comparison/compare_c++20.cc create mode 100644 libstdc++-v3/testsuite/20_util/unique_ptr/creation/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/uses_allocator/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/20_util/variant/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/21_strings/basic_string_view/operations/ [...] create mode 100644 libstdc++-v3/testsuite/21_strings/basic_string_view/operations/ [...] create mode 100644 libstdc++-v3/testsuite/23_containers/deque/modifiers/emplace/92 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/forward_list/modifiers/928 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/list/modifiers/emplace/928 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/map/modifiers/emplace/9287 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/multimap/modifiers/emplace [...] create mode 100644 libstdc++-v3/testsuite/23_containers/multiset/modifiers/emplace [...] create mode 100644 libstdc++-v3/testsuite/23_containers/priority_queue/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/23_containers/queue/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/23_containers/set/modifiers/emplace/9287 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/stack/92878_92947.cc create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_map/modifiers/92 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_multimap/modifie [...] create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_multiset/modifie [...] create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_set/modifiers/92 [...] create mode 100644 libstdc++-v3/testsuite/23_containers/vector/modifiers/emplace/9 [...] create mode 100644 libstdc++-v3/testsuite/24_iterators/back_insert_iterator/constexpr.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/front_insert_iterator/constexpr.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/insert_iterator/constexpr.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/move_iterator/input_iterator.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/move_iterator/move_only.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/move_iterator/rel_ops_c++20.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/slice/compare.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/generic/94242.cc create mode 100644 libstdc++-v3/testsuite/30_threads/condition_variable/members/cl [...] create mode 100644 libstdc++-v3/testsuite/30_threads/condition_variable_any/member [...] create mode 100644 libstdc++-v3/testsuite/30_threads/future/members/clock_neg.cc create mode 100644 libstdc++-v3/testsuite/30_threads/recursive_timed_mutex/try_loc [...] create mode 100644 libstdc++-v3/testsuite/30_threads/shared_future/members/clock_neg.cc create mode 100644 libstdc++-v3/testsuite/30_threads/shared_lock/locking/clock_neg.cc create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_u [...] create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_u [...] create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/try_lock_u [...] create mode 100644 libstdc++-v3/testsuite/30_threads/timed_mutex/try_lock_until/cl [...] create mode 100644 libstdc++-v3/testsuite/30_threads/unique_lock/locking/clock_neg.cc create mode 100644 libstdc++-v3/testsuite/experimental/net/execution_context/make_ [...] create mode 100644 libstdc++-v3/testsuite/experimental/net/executor/1.cc create mode 100644 libstdc++-v3/testsuite/std/time/clock/file/members.cc create mode 100644 libstdc++-v3/testsuite/std/time/clock/file/overview.cc create mode 100644 libstdc++-v3/testsuite/std/time/syn_c++20.cc create mode 100644 libstdc++-v3/testsuite/std/time/traits/is_clock.cc