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from 83bb288faa3 AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS new a992164c289 RISC-V: Fix missing implied Zicsr from Zve32x new e5d1f538bb7 RISC-V: Allow different dynamic floating point mode to be m [...]

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 1 + gcc/config/riscv/riscv.cc | 37 ++++++++++++++++++++++++++++++ gcc/testsuite/g++.target/riscv/pr119832.C | 27 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/predef-19.c | 34 ++++++--------------------- 4 files changed, 72 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/pr119832.C