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from 65f27c18e34 [RISC-V] Clear both upper and lower bits using 3 shifts new a4f45de95ee iesFrom: Alexandre Oliva oliva@adacore.com

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Summary of changes: gcc/config/aarch64/aarch64-vxworks.h | 7 +++---- gcc/config/aarch64/aarch64.cc | 21 ++++++++++++++++++--- gcc/testsuite/gcc.dg/cwsc1.c | 6 +++++- gcc/testsuite/gcc.target/aarch64/reg-alloc-4.c | 2 ++ .../gcc.target/aarch64/shadow_call_stack_1.c | 4 +++- .../gcc.target/aarch64/shadow_call_stack_2.c | 1 + .../gcc.target/aarch64/shadow_call_stack_3.c | 1 + .../gcc.target/aarch64/shadow_call_stack_4.c | 1 + .../gcc.target/aarch64/shadow_call_stack_5.c | 1 + .../gcc.target/aarch64/shadow_call_stack_6.c | 1 + .../gcc.target/aarch64/shadow_call_stack_7.c | 1 + .../gcc.target/aarch64/shadow_call_stack_8.c | 1 + .../gcc.target/aarch64/stack-check-prologue-19.c | 1 + .../gcc.target/aarch64/stack-check-prologue-20.c | 1 + 14 files changed, 40 insertions(+), 9 deletions(-)