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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2 in repository toolchain/ci/llvm-project.

from accc07e65465 [DAG] Fold (X & Y) != 0 --> zextOrTrunc(X & Y) iff everyth [...] adds 0b799791807e [RISCV] Merge some rvv intrinsic test cases that only diff [...]

No new revisions were added by this update.

Summary of changes: llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll | 1356 -------------------- .../CodeGen/RISCV/rvv/{vfadd-rv32.ll => vfadd.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll | 692 ---------- .../RISCV/rvv/{vfclass-rv32.ll => vfclass.ll} | 186 +-- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll | 617 --------- .../RISCV/rvv/{vfcvt-f-x-rv32.ll => vfcvt-f-x.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll | 617 --------- .../rvv/{vfcvt-f-xu-rv32.ll => vfcvt-f-xu.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll | 617 --------- .../{vfcvt-rtz-x-f-rv64.ll => vfcvt-rtz-x-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll | 617 --------- .../{vfcvt-rtz-xu-f-rv32.ll => vfcvt-rtz-xu-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll | 617 --------- .../RISCV/rvv/{vfcvt-x-f-rv32.ll => vfcvt-x-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll | 617 --------- .../rvv/{vfcvt-xu-f-rv32.ll => vfcvt-xu-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll | 1355 ------------------- .../CodeGen/RISCV/rvv/{vfdiv-rv32.ll => vfdiv.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll | 1106 ---------------- .../RISCV/rvv/{vfmacc-rv64.ll => vfmacc.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfmadd-rv32.ll => vfmadd.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll | 1355 ------------------- .../CodeGen/RISCV/rvv/{vfmax-rv64.ll => vfmax.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll | 902 ------------- .../RISCV/rvv/{vfmerge-rv64.ll => vfmerge.ll} | 246 ++-- llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll | 1355 ------------------- .../CodeGen/RISCV/rvv/{vfmin-rv64.ll => vfmin.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfmsac-rv32.ll => vfmsac.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfmsub-rv32.ll => vfmsub.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll | 1355 ------------------- .../CodeGen/RISCV/rvv/{vfmul-rv32.ll => vfmul.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll | 197 --- .../RISCV/rvv/{vfmv.s.f-rv32.ll => vfmv.s.f.ll} | 95 +- llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 482 ------- .../RISCV/rvv/{vfmv.v.f-rv32.ll => vfmv.v.f.ll} | 156 +-- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll | 380 ------ .../rvv/{vfncvt-f-f-rv32.ll => vfncvt-f-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll | 380 ------ .../rvv/{vfncvt-f-x-rv32.ll => vfncvt-f-x.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll | 380 ------ .../rvv/{vfncvt-f-xu-rv32.ll => vfncvt-f-xu.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll | 380 ------ .../{vfncvt-rod-f-f-rv32.ll => vfncvt-rod-f-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll | 632 --------- .../{vfncvt-rtz-x-f-rv32.ll => vfncvt-rtz-x-f.ll} | 216 ++-- .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll | 632 --------- ...{vfncvt-rtz-xu-f-rv32.ll => vfncvt-rtz-xu-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll | 632 --------- .../rvv/{vfncvt-x-f-rv32.ll => vfncvt-x-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll | 632 --------- .../rvv/{vfncvt-xu-f-rv32.ll => vfncvt-xu-f.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfnmacc-rv32.ll => vfnmacc.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfnmadd-rv32.ll => vfnmadd.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll | 1106 ---------------- .../RISCV/rvv/{vfnmsac-rv32.ll => vfnmsac.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll | 1106 ---------------- .../RISCV/rvv/{vfnmsub-rv64.ll => vfnmsub.ll} | 294 ++--- llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll | 677 ---------- .../RISCV/rvv/{vfrdiv-rv32.ll => vfrdiv.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll | 617 --------- .../RISCV/rvv/{vfrec7-rv32.ll => vfrec7.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 692 ---------- .../RISCV/rvv/{vfredmax-rv32.ll => vfredmax.ll} | 186 +-- llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 692 ---------- .../RISCV/rvv/{vfredmin-rv32.ll => vfredmin.ll} | 186 +-- llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 692 ---------- .../RISCV/rvv/{vfredosum-rv32.ll => vfredosum.ll} | 186 +-- llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll | 692 ---------- .../RISCV/rvv/{vfredusum-rv32.ll => vfredusum.ll} | 186 +-- llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll | 617 --------- .../RISCV/rvv/{vfrsqrt7-rv32.ll => vfrsqrt7.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll | 678 ---------- .../RISCV/rvv/{vfrsub-rv32.ll => vfrsub.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll | 1355 ------------------- .../RISCV/rvv/{vfsgnj-rv32.ll => vfsgnj.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll | 1355 ------------------- .../RISCV/rvv/{vfsgnjn-rv32.ll => vfsgnjn.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll | 1355 ------------------- .../RISCV/rvv/{vfsgnjx-rv32.ll => vfsgnjx.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll | 677 ---------- .../rvv/{vfslide1down-rv32.ll => vfslide1down.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll | 692 ---------- .../rvv/{vfslide1up-rv32.ll => vfslide1up.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll | 548 -------- .../RISCV/rvv/{vfsqrt-rv64.ll => vfsqrt.ll} | 306 ++--- llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll | 1356 -------------------- .../CodeGen/RISCV/rvv/{vfsub-rv32.ll => vfsub.ll} | 426 +++--- llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwadd-rv32.ll => vfwadd.ll} | 258 ++-- llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll | 1248 ------------------ .../RISCV/rvv/{vfwadd.w-rv32.ll => vfwadd.w.ll} | 362 +++--- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll | 380 ------ .../rvv/{vfwcvt-f-f-rv32.ll => vfwcvt-f-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll | 632 --------- .../rvv/{vfwcvt-f-x-rv32.ll => vfwcvt-f-x.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll | 632 --------- .../rvv/{vfwcvt-f-xu-rv32.ll => vfwcvt-f-xu.ll} | 216 ++-- llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll | 380 ------ .../{vfwcvt-rtz-x-f-rv32.ll => vfwcvt-rtz-x-f.ll} | 132 +- .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll | 380 ------ ...{vfwcvt-rtz-xu-f-rv64.ll => vfwcvt-rtz-xu-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll | 380 ------ .../rvv/{vfwcvt-x-f-rv32.ll => vfwcvt-x-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll | 380 ------ .../rvv/{vfwcvt-xu-f-rv32.ll => vfwcvt-xu-f.ll} | 132 +- llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwmacc-rv32.ll => vfwmacc.ll} | 222 ++-- llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwmsac-rv32.ll => vfwmsac.ll} | 222 ++-- llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll | 830 ------------ .../RISCV/rvv/{vfwmul-rv64.ll => vfwmul.ll} | 258 ++-- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwnmacc-rv32.ll => vfwnmacc.ll} | 222 ++-- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwnmsac-rv32.ll => vfwnmsac.ll} | 222 ++-- llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll | 508 -------- .../rvv/{vfwredosum-rv32.ll => vfwredosum.ll} | 138 +- llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll | 508 -------- .../rvv/{vfwredusum-rv32.ll => vfwredusum.ll} | 138 +- llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll | 830 ------------ .../RISCV/rvv/{vfwsub-rv32.ll => vfwsub.ll} | 258 ++-- llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll | 1248 ------------------ .../RISCV/rvv/{vfwsub.w-rv64.ll => vfwsub.w.ll} | 362 +++--- 128 files changed, 7848 insertions(+), 58637 deletions(-) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfadd-rv32.ll => vfadd.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfclass-rv32.ll => vfclass.ll} (91%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-f-x-rv32.ll => vfcvt-f-x.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-f-xu-rv32.ll => vfcvt-f-xu.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-rtz-x-f-rv64.ll => vfcvt-rtz-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-rtz-xu-f-rv32.ll => vfcvt-rtz-xu-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-x-f-rv32.ll => vfcvt-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfcvt-xu-f-rv32.ll => vfcvt-xu-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfdiv-rv32.ll => vfdiv.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmacc-rv64.ll => vfmacc.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmadd-rv32.ll => vfmadd.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmax-rv64.ll => vfmax.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmerge-rv64.ll => vfmerge.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmin-rv64.ll => vfmin.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmsac-rv32.ll => vfmsac.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmsub-rv32.ll => vfmsub.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmul-rv32.ll => vfmul.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmv.s.f-rv32.ll => vfmv.s.f.ll} (74%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfmv.v.f-rv32.ll => vfmv.v.f.ll} (82%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-f-f-rv32.ll => vfncvt-f-f.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-f-x-rv32.ll => vfncvt-f-x.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-f-xu-rv32.ll => vfncvt-f-xu.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-rod-f-f-rv32.ll => vfncvt-rod-f-f.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-rtz-x-f-rv32.ll => vfncvt-rtz-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-rtz-xu-f-rv32.ll => vfncvt-rtz-xu-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-x-f-rv32.ll => vfncvt-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfncvt-xu-f-rv32.ll => vfncvt-xu-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfnmacc-rv32.ll => vfnmacc.ll} (90%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfnmadd-rv32.ll => vfnmadd.ll} (90%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfnmsac-rv32.ll => vfnmsac.ll} (90%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfnmsub-rv64.ll => vfnmsub.ll} (90%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfrdiv-rv32.ll => vfrdiv.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfrec7-rv32.ll => vfrec7.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfredmax-rv32.ll => vfredmax.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfredmin-rv32.ll => vfredmin.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfredosum-rv32.ll => vfredosum.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredusum-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfredusum-rv32.ll => vfredusum.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfrsqrt7-rv32.ll => vfrsqrt7.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfrsub-rv32.ll => vfrsub.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfsgnj-rv32.ll => vfsgnj.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfsgnjn-rv32.ll => vfsgnjn.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfsgnjx-rv32.ll => vfsgnjx.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfslide1down-rv32.ll => vfslide1down.ll} (85%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfslide1up-rv32.ll => vfslide1up.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfsqrt-rv64.ll => vfsqrt.ll} (80%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfsub-rv32.ll => vfsub.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwadd-rv32.ll => vfwadd.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwadd.w-rv32.ll => vfwadd.w.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-f-f-rv32.ll => vfwcvt-f-f.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-f-x-rv32.ll => vfwcvt-f-x.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-f-xu-rv32.ll => vfwcvt-f-xu.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-rtz-x-f-rv32.ll => vfwcvt-rtz-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-rtz-xu-f-rv64.ll => vfwcvt-rtz-xu-f.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-x-f-rv32.ll => vfwcvt-x-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwcvt-xu-f-rv32.ll => vfwcvt-xu-f.ll} (87%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwmacc-rv32.ll => vfwmacc.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwmsac-rv32.ll => vfwmsac.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwmul-rv64.ll => vfwmul.ll} (86%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwnmacc-rv32.ll => vfwnmacc.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwnmsac-rv32.ll => vfwnmsac.ll} (89%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwredosum-rv32.ll => vfwredosum.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwredusum-rv32.ll => vfwredusum.ll} (88%) delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll rename llvm/test/CodeGen/RISCV/rvv/{vfwsub-rv32.ll => vfwsub.ll} (86%) delete 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