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from 218a20ac21c [AArch64] Fix condition for "high-vector" DUP optimizations. new 5e75b645f6e [X86] Add FPCW as a register and start using it as an impli [...]

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Summary of changes: lib/Target/X86/X86InstrFPStack.td | 56 +++++++++++++++----------------- lib/Target/X86/X86RegisterInfo.cpp | 3 ++ lib/Target/X86/X86RegisterInfo.td | 3 ++ test/CodeGen/MIR/X86/memory-operands.mir | 4 +-- test/CodeGen/X86/ipra-reg-usage.ll | 2 +- test/CodeGen/X86/pr34080.ll | 4 +-- test/CodeGen/X86/pr40529.ll | 4 +-- 7 files changed, 40 insertions(+), 36 deletions(-)