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- Log ----------------------------------------------------------------- commit 257ea32277aa257c85e1e22b2e2e9b07da436938 Author: alalaw01 alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4 Date: Mon Jul 6 17:32:07 2015 +0000

2015-07-06 Alan Lawrence alan.lawrence@arm.com

Backport from mainline r225465 2015-07-06 Alan Lawrence alan.lawrence@arm.com

gcc/:

PR target/65956 * config/arm/arm.c (arm_needs_doubleword_align): Drop any outer alignment attribute, exploring one level down for records and arrays.

gcc/testsuite/:

* gcc.target/arm/aapcs/align1.c: New. * gcc.target/arm/aapcs/align_rec1.c: New. * gcc.target/arm/aapcs/align2.c: New. * gcc.target/arm/aapcs/align_rec2.c: New. * gcc.target/arm/aapcs/align3.c: New. * gcc.target/arm/aapcs/align_rec3.c: New. * gcc.target/arm/aapcs/align4.c: New. * gcc.target/arm/aapcs/align_rec4.c: New. * gcc.target/arm/aapcs/align_vararg1.c: New. * gcc.target/arm/aapcs/align_vararg2.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@225469 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 84cc4ff..10c8055 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2015-07-06 Alan Lawrence alan.lawrence@arm.com

+ Backport from mainline r225465 + 2015-07-06 Alan Lawrence alan.lawrence@arm.com + + PR target/65956 + * config/arm/arm.c (arm_needs_doubleword_align): Drop any outer + alignment attribute, exploring one level down for records and arrays. + +2015-07-06 Alan Lawrence alan.lawrence@arm.com + Backport from mainline r225461 2015-07-06 Alan Lawrence alan.lawrence@arm.com

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 292fed9..fb14891 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -6020,8 +6020,23 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, static bool arm_needs_doubleword_align (machine_mode mode, const_tree type) { - return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY - || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); + if (!type) + return PARM_BOUNDARY < GET_MODE_ALIGNMENT (mode); + + /* Scalar and vector types: Use natural alignment, i.e. of base type. */ + if (!AGGREGATE_TYPE_P (type)) + return TYPE_ALIGN (TYPE_MAIN_VARIANT (type)) > PARM_BOUNDARY; + + /* Array types: Use member alignment of element type. */ + if (TREE_CODE (type) == ARRAY_TYPE) + return TYPE_ALIGN (TREE_TYPE (type)) > PARM_BOUNDARY; + + /* Record/aggregate types: Use greatest member alignment of any member. */ + for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) + if (DECL_ALIGN (field) > PARM_BOUNDARY) + return true; + + return false; }

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 020d4de..98cefd1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,19 @@ +2015-07-06 Alan Lawrence alan.lawrence@arm.com + + Backport from mainline r225465 + 2015-07-06 Alan Lawrence alan.lawrence@arm.com + + * gcc.target/arm/aapcs/align1.c: New. + * gcc.target/arm/aapcs/align_rec1.c: New. + * gcc.target/arm/aapcs/align2.c: New. + * gcc.target/arm/aapcs/align_rec2.c: New. + * gcc.target/arm/aapcs/align3.c: New. + * gcc.target/arm/aapcs/align_rec3.c: New. + * gcc.target/arm/aapcs/align4.c: New. + * gcc.target/arm/aapcs/align_rec4.c: New. + * gcc.target/arm/aapcs/align_vararg1.c: New. + * gcc.target/arm/aapcs/align_vararg2.c: New. + 2015-07-05 Bill Schmidt wschmidt@linux.vnet.ibm.com

Backport from mainline r224725 diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align1.c b/gcc/testsuite/gcc.target/arm/aapcs/align1.c new file mode 100644 index 0000000..8981d57 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align1.c @@ -0,0 +1,29 @@ +/* Test AAPCS layout (alignment). */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O" } */ + +#ifndef IN_FRAMEWORK +#define TESTFILE "align1.c" + +typedef __attribute__((aligned (8))) int alignedint; + +alignedint a = 11; +alignedint b = 13; +alignedint c = 17; +alignedint d = 19; +alignedint e = 23; +alignedint f = 29; + +#include "abitest.h" +#else + ARG (alignedint, a, R0) + /* Attribute suggests R2, but we should use only natural alignment: */ + ARG (alignedint, b, R1) + ARG (alignedint, c, R2) + ARG (alignedint, d, R3) + ARG (alignedint, e, STACK) + /* Attribute would suggest STACK + 8 but should be ignored: */ + LAST_ARG (alignedint, f, STACK + 4) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align2.c b/gcc/testsuite/gcc.target/arm/aapcs/align2.c new file mode 100644 index 0000000..992da53 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align2.c @@ -0,0 +1,30 @@ +/* Test AAPCS layout (alignment). */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O" } */ + +#ifndef IN_FRAMEWORK +#define TESTFILE "align2.c" + +/* The underlying struct here has alignment 4. */ +typedef struct __attribute__((aligned (8))) + { + int x; + int y; + } overaligned; + +/* A couple of instances, at 8-byte-aligned memory locations. */ +overaligned a = { 2, 3 }; +overaligned b = { 5, 8 }; + +#include "abitest.h" +#else + ARG (int, 7, R0) + /* Alignment should be 4. */ + ARG (overaligned, a, R1) + ARG (int, 9, R3) + ARG (int, 10, STACK) + /* Alignment should be 4. */ + LAST_ARG (overaligned, b, STACK + 4) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align3.c b/gcc/testsuite/gcc.target/arm/aapcs/align3.c new file mode 100644 index 0000000..81ad3f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align3.c @@ -0,0 +1,42 @@ +/* Test AAPCS layout (alignment). */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O3" } */ + +#ifndef IN_FRAMEWORK +#define TESTFILE "align3.c" + +/* Struct will be aligned to 8. */ +struct s + { + int x; + /* 4 bytes padding here. */ + __attribute__((aligned (8))) int y; + /* 4 bytes padding here. */ + }; + +typedef struct s __attribute__((aligned (4))) underaligned; + +#define EXPECTED_STRUCT_SIZE 16 +extern void link_failure (void); +int +foo () +{ + /* Optimization gets rid of this before linking. */ + if (sizeof (struct s) != EXPECTED_STRUCT_SIZE) + link_failure (); +} + +underaligned a = { 1, 4 }; +underaligned b = { 9, 16 }; + +#include "abitest.h" +#else + ARG (int, 3, R0) + /* Object alignment is 8, so split between 2 regs and 8 on stack. */ + ARG (underaligned, a, R2) + ARG (int, 6, STACK + 8) + /* Object alignment is 8, so skip over STACK + 12. */ + LAST_ARG (underaligned, b, STACK + 16) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align4.c b/gcc/testsuite/gcc.target/arm/aapcs/align4.c new file mode 100644 index 0000000..5535c55 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align4.c @@ -0,0 +1,29 @@ +/* Test AAPCS layout (alignment) - passing vectors in GPRs. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O" } */ +/* { dg-add-options arm_neon } */ + +#ifndef IN_FRAMEWORK +#define TESTFILE "align4.c" + +#define PCSATTR __attribute__((pcs("aapcs"))) + +#include <arm_neon.h> + +typedef __attribute__((aligned (4))) int32x2_t unalignedvec; + +unalignedvec a = {11, 13}; +unalignedvec b = {17, 19}; + +#include "abitest.h" +#else + ARG (int, 2, R0) + /* Attribute suggests R1, but we should use natural alignment: */ + ARG (unalignedvec, a, R2) + ARG (int, 6, STACK) + /* Attribute would suggest STACK + 4 but should be ignored: */ + LAST_ARG (unalignedvec, b, STACK + 8) +#endif diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_rec1.c b/gcc/testsuite/gcc.target/arm/aapcs/align_rec1.c new file mode 100644 index 0000000..2e42bae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_rec1.c @@ -0,0 +1,36 @@ +/* Test AAPCS layout (alignment) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -fno-inline" } */ + +extern void abort (void); + +typedef __attribute__((aligned (8))) int alignedint; + +alignedint a = 11; +alignedint b = 13; +alignedint c = 17; +alignedint d = 19; +alignedint e = 23; +alignedint f = 29; + +void +foo (alignedint r0, alignedint r1, alignedint r2, alignedint r3, + alignedint stack, alignedint stack4) +{ + if (r0 != a + || r1 != b + || r2 != c + || r3 != d + || stack != e + || stack4 !=f) + abort (); +} + +int +main (int argc, char **argv) +{ + foo (a, b, c, d, e, f); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_rec2.c b/gcc/testsuite/gcc.target/arm/aapcs/align_rec2.c new file mode 100644 index 0000000..a00da50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_rec2.c @@ -0,0 +1,41 @@ +/* Test AAPCS layout (alignment) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -fno-inline" } */ + +extern int memcmp (const void *s1, const void *s2, __SIZE_TYPE__ n); +extern void abort (void); + +typedef struct __attribute__((aligned (8))) + { + int x; + int y; + } overaligned; + +overaligned a = { 2, 3 }; +overaligned b = { 5, 8 }; + +void +f (int r0, overaligned r1, int r3, int stack, overaligned stack4) +{ + if (r0 != 7 || r3 != 9 || stack != 10) + abort (); + if (memcmp ((void *) &r1, (void *)&a, sizeof (overaligned))) + abort (); + if (memcmp ((void *)&stack4, (void *)&b, sizeof (overaligned))) + abort (); + int addr = ((int) &stack4) & 7; + if (addr != 0) + { + __builtin_printf ("Alignment was %d\n", addr); + abort (); + } +} + +int +main (int argc, char **argv) +{ + f (7, a, 9, 10, b); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_rec3.c b/gcc/testsuite/gcc.target/arm/aapcs/align_rec3.c new file mode 100644 index 0000000..2184cb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_rec3.c @@ -0,0 +1,43 @@ +/* Test AAPCS layout (alignment) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -fno-inline" } */ + +/* Test AAPCS layout (alignment) for callee. */ + +extern int memcmp (const void *s1, const void *s2, __SIZE_TYPE__ n); +extern void abort (void); + + +/* Struct will be aligned to 8. */ +struct s + { + int x; + /* 4 bytes padding here. */ + __attribute__((aligned (8))) int y; + /* 4 bytes padding here. */ + }; + +typedef struct s __attribute__((aligned (4))) underaligned; + +underaligned a = { 1, 4 }; +underaligned b = { 9, 16 }; + +void +f (int r0, underaligned r2, int stack8, underaligned stack16) +{ + if (r0 != 3 || stack8 != 6) + abort (); + if (memcmp ((void *) &r2, (void *)&a, sizeof (underaligned))) + abort (); + if (memcmp ((void *)&stack16, (void *)&b, sizeof (underaligned))) + abort (); +} + +int +main (int argc, char **argv) +{ + f (3, a, 6, b); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_rec4.c b/gcc/testsuite/gcc.target/arm/aapcs/align_rec4.c new file mode 100644 index 0000000..907b90a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_rec4.c @@ -0,0 +1,33 @@ +/* Test AAPCS layout (alignment) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> + +extern int memcmp (const void *s1, const void *s2, __SIZE_TYPE__ n); +extern void abort (void); + +typedef __attribute__((aligned (4))) int32x4_t unalignedvec; + +unalignedvec a = {11, 13}; +unalignedvec b = {17, 19}; + +void +foo (int r0, unalignedvec r2, int s0, unalignedvec s8) +{ + if (r0 != 2 || s0 != 6 + || memcmp ( (void *) &r2, (void *) &a, 16) + || memcmp ( (void *) &s8, (void *) &b, 16)) + abort (); +} + +int +main (int argc, char **argv) +{ + foo (2, a, 6, b); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg1.c b/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg1.c new file mode 100644 index 0000000..daa3214 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg1.c @@ -0,0 +1,36 @@ +/* Test AAPCS layout (alignment of varargs) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -fno-inline" } */ + +#include <stdarg.h> + +extern void abort (void); + +typedef __attribute__((aligned (8))) int alignedint; + +void +foo (int i, ...) +{ + va_list va; + va_start (va, i); + /* Arguments should be passed in the same registers as if they were ints. */ + while (i-- > 0) + if (va_arg (va, int) != i) + abort (); + va_end (va); +} + +int +main (int argc, char **argv) +{ + alignedint a = 5; + alignedint b = 4; + alignedint c = 3; + alignedint d = 2; + alignedint e = 1; + alignedint f = 0; + foo (a, b, c, d, e, f); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg2.c b/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg2.c new file mode 100644 index 0000000..b0c923b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/aapcs/align_vaarg2.c @@ -0,0 +1,30 @@ +/* Test AAPCS layout (alignment of varargs) for callee. */ + +/* { dg-do run { target arm_eabi } } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -fno-inline" } */ + +#include <stdarg.h> + +extern void abort (void); + +typedef __attribute__((aligned (8))) int alignedint; + +void +foo (int i, ...) +{ + va_list va; + va_start (va, i); + /* alignedint should be pulled out of regs/stack just like an int. */ + while (i-- > 0) + if (va_arg (va, alignedint) != i) + abort (); + va_end (va); +} + +int +main (int argc, char **argv) +{ + foo (5, 4, 3, 2, 1, 0); + return 0; +}

commit 8778b301b35bdbcbedbf3a01e287af1a7e7513e4 Author: alalaw01 alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4 Date: Mon Jul 6 17:18:40 2015 +0000

2015-07-06 Alan Lawrence alan.lawrence@arm.com

Backport from mainline r225461 2015-07-06 Alan Lawrence alan.lawrence@arm.com

* config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-5-branch@225467 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 57cc341..84cc4ff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-07-06 Alan Lawrence alan.lawrence@arm.com + + Backport from mainline r225461 + 2015-07-06 Alan Lawrence alan.lawrence@arm.com + + * config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state. + 2015-07-05 Bill Schmidt wschmidt@linux.vnet.ibm.com

Backport from mainline r224725 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c931e56..f63fc39 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5415,6 +5415,42 @@ if (!REG_P (operands[0])) operands[1] = force_reg (DImode, operands[1]); } + if (REG_P (operands[0]) && REGNO (operands[0]) < FIRST_VIRTUAL_REGISTER + && !HARD_REGNO_MODE_OK (REGNO (operands[0]), DImode)) + { + /* Avoid LDRD's into an odd-numbered register pair in ARM state + when expanding function calls. */ + gcc_assert (can_create_pseudo_p ()); + if (MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1])) + { + /* Perform load into legal reg pair first, then move. */ + rtx reg = gen_reg_rtx (DImode); + emit_insn (gen_movdi (reg, operands[1])); + operands[1] = reg; + } + emit_move_insn (gen_lowpart (SImode, operands[0]), + gen_lowpart (SImode, operands[1])); + emit_move_insn (gen_highpart (SImode, operands[0]), + gen_highpart (SImode, operands[1])); + DONE; + } + else if (REG_P (operands[1]) && REGNO (operands[1]) < FIRST_VIRTUAL_REGISTER + && !HARD_REGNO_MODE_OK (REGNO (operands[1]), DImode)) + { + /* Avoid STRD's from an odd-numbered register pair in ARM state + when expanding function prologue. */ + gcc_assert (can_create_pseudo_p ()); + rtx split_dest = (MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0])) + ? gen_reg_rtx (DImode) + : operands[0]; + emit_move_insn (gen_lowpart (SImode, split_dest), + gen_lowpart (SImode, operands[1])); + emit_move_insn (gen_highpart (SImode, split_dest), + gen_highpart (SImode, operands[1])); + if (split_dest != operands[0]) + emit_insn (gen_movdi (operands[0], split_dest)); + DONE; + } " )

-----------------------------------------------------------------------

Summary of changes: gcc/ChangeLog | 16 +++++++++ gcc/config/arm/arm.c | 19 ++++++++-- gcc/config/arm/arm.md | 36 +++++++++++++++++++ gcc/testsuite/ChangeLog | 16 +++++++++ gcc/testsuite/gcc.target/arm/aapcs/align1.c | 29 +++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align2.c | 30 ++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align3.c | 42 ++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align4.c | 29 +++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_rec1.c | 36 +++++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_rec2.c | 41 +++++++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_rec3.c | 43 +++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_rec4.c | 33 +++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_vaarg1.c | 36 +++++++++++++++++++ gcc/testsuite/gcc.target/arm/aapcs/align_vaarg2.c | 30 ++++++++++++++++ 14 files changed, 434 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align1.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align2.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align3.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align4.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_rec1.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_rec2.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_rec3.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_rec4.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_vaarg1.c create mode 100644 gcc/testsuite/gcc.target/arm/aapcs/align_vaarg2.c

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