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from 9a07ac15132 PR 89213: Add better support for shifting vectors with 64-b [...] new a82896ed7bb RISC-V: Implement SAT_ADD for signed integer vector

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Summary of changes: gcc/config/riscv/autovec.md | 11 + gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 9 + .../riscv/rvv/autovec/binop/vec_sat_data.h | 264 +++++++++++++++++++++ .../{vec_sat_u_add-25.c => vec_sat_s_add-1.c} | 6 +- .../{vec_sat_u_add-26.c => vec_sat_s_add-2.c} | 6 +- .../{vec_sat_u_add-27.c => vec_sat_s_add-3.c} | 6 +- .../{vec_sat_u_add-28.c => vec_sat_s_add-4.c} | 6 +- .../riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c | 17 ++ .../riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c | 17 ++ .../riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c | 17 ++ .../riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c | 17 ++ .../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 25 ++ 13 files changed, 390 insertions(+), 12 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-25.c => vec_s [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-26.c => vec_s [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-27.c => vec_s [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vec_sat_u_add-28.c => vec_s [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c