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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project.

from e2321bb4488 [SLP] avoid reduction transform on patterns that the backen [...] adds 8815be04ec1 [X86][AVX] Push sign extensions of comparison bool results [...] adds 2decdf42b95 [FastISel] Copy the inline assembly dialect to the INLINEAS [...] adds 69c65a86097 AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics adds a5b9c756745 GlobalISel: Partially implement lower for G_EXTRACT adds bcd6b1d2090 AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESS adds c0ec72d4f85 AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics adds 786a3953bac AMDGPU/GlobalISel: RegBankSelect mul24 intrinsics adds e59296a0519 AMDGPU/GlobalISel: Fall back on weird G_EXTRACT offsets adds c209598268b [clang-format][docs] Fix the Google C++ and Chromium style [...] adds 7653ff398d2 [X86] Enable AVX512BW for memcmp() adds 032dd9b086c [X86][SSE] matchVectorShuffleAsBlend - use Zeroable element [...] adds c38881a6b7f [InstCombine] don't assume 'inbounds' for bitcast pointer t [...] adds 61c22a83dee [InstCombine] add fast-math-flags for better test coverage; NFC adds 2dee7e55610 [X86][AVX] combineExtractSubvector - merge duplicate variab [...] adds 25ba49824d2 [DAGCombine] Match more patterns for half word bswap adds aab8b3ab9cf [InstCombine] fold fneg disguised as select+fmul (PR43497) adds ee68f1ec67c [NFC] Replace 'isDarwin' with 'IsDarwin' adds f643fabb525 Revert [DAGCombine] Match more patterns for half word bswap adds 6d196514104 [Docs] Adds new Getting Started/Tutorials page adds 5c876303ecd [X86][SSE] resolveTargetShuffleInputs - call getTargetShuff [...] adds de0e3aac2a2 [Docs] Removes Programming Documentation page adds dcb75bf843e [LOOPGUARD] Remove asserts in getLoopGuardBranch Summary: T [...] adds 598e7a3a689 gn build: make windows build less broken adds 1e9c0cecab5 [Sema] Avoids an assertion failure when an invalid conversi [...] adds 842dde6be43 [LegalizeTypes][X86] When splitting a vselect for type lega [...] adds 570ae49d030 [X86] Add custom type legalization for v16i64->v16i8 trunca [...] adds 344df110e56 Implements CWG 1601 in [over.ics.rank/4.2] new 42010dc8108 [X86][SSE] Don't merge known undef/zero elements into targe [...] new 739c9f0b793 [X86][SSE] Remove resolveTargetShuffleInputs and use getTar [...] new e36415cacff [NFC][PowerPC] Reorganize CRNotPat multiclass patterns in P [...] new d84cd7caa87 Fix signed/unsigned warning. NFCI

The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang/docs/ClangFormatStyleOptions.rst | 2 +- clang/lib/Sema/SemaDecl.cpp | 3 + clang/lib/Sema/SemaOverload.cpp | 42 +++ clang/test/CXX/drs/dr16xx.cpp | 12 + clang/test/CXX/drs/dr6xx.cpp | 15 +- clang/test/CodeGen/aapcs-bitfield.c | 72 ++--- .../test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp | 16 +- clang/test/CodeGenCXX/microsoft-abi-typeid.cpp | 2 +- clang/test/SemaCXX/PR31422.cpp | 7 + clang/www/cxx_dr_status.html | 2 +- llvm/docs/GettingStartedTutorials.rst | 34 +++ llvm/docs/ProgrammingDocumentation.rst | 67 ----- llvm/docs/Reference.rst | 120 +++++++-- llvm/docs/SubsystemDocumentation.rst | 46 +--- llvm/docs/UserGuides.rst | 103 +++++--- llvm/docs/index.rst | 33 +-- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + llvm/lib/Analysis/LoopInfo.cpp | 12 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 35 +++ llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 1 + .../CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp | 15 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 17 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 48 +++- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.cpp | 4 +- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h | 14 +- llvm/lib/Target/PowerPC/PPC.h | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 20 +- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 175 ++++++------ llvm/lib/Target/PowerPC/PPCMCInstLower.cpp | 22 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 294 +++++++++++---------- .../Transforms/InstCombine/InstCombineCasts.cpp | 11 +- .../InstCombine/InstCombineMulDivRem.cpp | 67 +++-- .../GlobalISel/artifact-combiner-extract.mir | 14 +- .../legalize-atomic-cmpxchg-with-success.mir | 107 ++++++++ .../GlobalISel/legalize-extract-vector-elt.mir | 20 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 183 ++++++++++++- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 20 +- .../regbankselect-amdgcn.ds.gws.init.mir | 79 ++++++ .../regbankselect-amdgcn.ds.gws.sema.v.mir | 37 +++ .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 13 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 15 +- .../AMDGPU/GlobalISel/regbankselect-constant.mir | 8 +- llvm/test/CodeGen/X86/avx512-vselect.ll | 59 ++--- llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 161 +++++------ llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll | 124 ++++----- llvm/test/CodeGen/X86/memcmp.ll | 20 +- llvm/test/CodeGen/X86/min-legal-vector-width.ll | 61 ++--- llvm/test/CodeGen/X86/packss.ll | 22 +- llvm/test/CodeGen/X86/pr34177.ll | 121 ++++++--- llvm/test/CodeGen/X86/pr43575.ll | 14 + llvm/test/CodeGen/X86/setcc-wide-types.ll | 118 ++++++--- llvm/test/CodeGen/X86/vector-trunc-packus.ll | 65 ++++- llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 59 ++++- llvm/test/CodeGen/X86/vector-trunc-usat.ll | 50 +++- llvm/test/Transforms/InstCombine/addrspacecast.ll | 2 +- llvm/test/Transforms/InstCombine/cast.ll | 4 +- llvm/test/Transforms/InstCombine/fmul.ll | 32 ++- .../Transforms/InstCombine/load-bitcast-vec.ll | 35 +++ llvm/test/Transforms/InstCombine/memset.ll | 2 +- llvm/test/Transforms/InstCombine/unpack-fca.ll | 18 +- llvm/unittests/Analysis/LoopInfoTest.cpp | 85 ++++++ llvm/utils/gn/build/toolchain/BUILD.gn | 3 + 65 files changed, 1901 insertions(+), 985 deletions(-) create mode 100644 clang/test/SemaCXX/PR31422.cpp create mode 100644 llvm/docs/GettingStartedTutorials.rst delete mode 100644 llvm/docs/ProgrammingDocumentation.rst create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-wit [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws [...] create mode 100644 llvm/test/CodeGen/X86/pr43575.ll