[gcc] branch master updated (9cc5521162e -> e030af3e6f6) - Tcwg-commits

28 Aug 2023


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from  9cc5521162e Daily bump.
       new  e030af3e6f6 RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS
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Summary of changes:
 gcc/config/riscv/riscv-vsetvl.cc                   | 1674 ++++++++------------
 gcc/config/riscv/riscv-vsetvl.h                    |   78 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c   |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c   |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-102.c   |    1 +
 .../vsetvl/{avl_single-50.c => avl_single-103.c}   |   10 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-14.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-15.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-27.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-28.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-29.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-30.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-35.c    |    1 +
 .../gcc.target/riscv/rvv/vsetvl/avl_single-36.c    |   14 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-46.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-48.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-50.c    |    5 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-51.c    |    5 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-6.c     |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-66.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-67.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-68.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-69.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-70.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-71.c    |    6 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-72.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-76.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-77.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-82.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-83.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-84.c    |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-89.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-93.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-94.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-95.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_single-96.c    |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/ffload-5.c         |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c    |    1 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c    |    1 +
 .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c    |    1 +
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-7.c     |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/imm_switch-9.c     |    4 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-45.c          |    1 -
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c  |   18 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c |    6 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c  |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c  |   18 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c  |    2 +-
 .../riscv/rvv/vsetvl/vlmax_conflict-13.c           |   20 +
 .../gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c |    2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c        |    2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c       |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c        |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c        |    3 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c      |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c      |    4 +-
 58 files changed, 800 insertions(+), 1175 deletions(-)
 copy gcc/testsuite/gcc.target/riscv/rvv/vsetvl/{avl_single-50.c => avl_single-103. [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
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