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from ea66f57c960 aarch64: Add mf8 data movement intrinsics new 64d31343d46 [RISC-V][PR target/118122] Fix modes in recently added risc [...]

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Summary of changes: gcc/config/riscv/riscv.md | 24 ++++++++++++------------ gcc/testsuite/gcc.target/riscv/pr118122.c | 12 ++++++++++++ 2 files changed, 24 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr118122.c