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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project.

from 2bdf33cc4c7 [mlir] NFC: Remove Value::operator* and Value::operator-> n [...] adds 4c48ea68e49 [ASTMatchers] extract public matchers from const-analysis i [...] adds 23a799adf0a Revert "[ASTMatchers] extract public matchers from const-an [...] adds d2751f8fdf6 [ExecutionEngine] Re-enable FastISel for non-iOS arm targets. adds dc422e968e7 Add -Wrange-loop-analysis changes to ReleaseNotes adds 9cc9120969f [X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/S [...] adds a5994c789a2 [X86][Disassembler] Simplify and optimize reader functions adds 9fe6f36c1a9 [LegalizeVectorOps] Only pass SDNode* instead SDValue to al [...] adds 5a9954c02a7 [LegalizeVectorOps] Remove some of the simpler Expand metho [...] adds 179abb091d8 [X86][Disassembler] Replace custom logger with LLVM_DEBUG adds a1f16998f37 [Support] Optionally call signal handlers when a function w [...] adds 2cdb18afda8 [ORC] Fix argv handling in runAsMain / lli. adds 6fdd6a7b3f6 [Disassembler] Delete the VStream parameter of MCDisassembl [...] adds 1e8ce7492e9 [X86][Disassembler] Optimize argument passing and immediate [...] adds f719c540bb0 [X86][Disassembler] Shrink X86GenDisassemblerTables.inc fro [...] adds ddfcd82bdc2 [LegalizeVectorOps] Expand vector MERGE_VALUES immediately. adds ed679804d5e [TargetLowering][X86] Connect the chain from STRICT_FSETCC [...] adds efb674ac2f2 [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UI [...] adds 569ccfc384a [SCEV] more accurate range for addrecexpr with nsw flag. adds d692f0f6c8c [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSE [...] adds f33fd43a7c9 [NFC] Refactor memory ops cluster method adds c5b94ea2651 [profile] Support merge pool size >= 10 adds 51c1d7c4bec [X86][Disassembler] Simplify adds 60cc095ecc3 [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X [...] adds b375f28b0ec [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the [...] adds 66e39067edb [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower b [...] adds 065eefcfe96 [AMDGPU] Regenerate shl shift tests adds a888277897f [MIPS] Regenerate shl/lshr shift tests adds ad201691d5c Fix "pointer is null" static analyzer warnings. NFCI.

No new revisions were added by this update.

Summary of changes: clang/docs/ReleaseNotes.rst | 4 + .../lib/StaticAnalyzer/Checkers/CStringChecker.cpp | 17 +- compiler-rt/lib/profile/InstrProfilingFile.c | 46 +- compiler-rt/test/profile/instrprof-basic.c | 7 + .../Disassembler/llvm/DisassemblerLLVMC.cpp | 2 +- .../Instruction/MIPS/EmulateInstructionMIPS.cpp | 18 +- .../MIPS64/EmulateInstructionMIPS64.cpp | 4 +- .../llvm/MC/MCDisassembler/MCDisassembler.h | 4 - llvm/include/llvm/Support/CrashRecoveryContext.h | 8 + llvm/include/llvm/Support/Signals.h | 9 + llvm/lib/Analysis/ScalarEvolution.cpp | 26 +- llvm/lib/CodeGen/MachineScheduler.cpp | 21 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 612 +++---- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 +- llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp | 2 +- .../RuntimeDyld/RuntimeDyldChecker.cpp | 2 +- llvm/lib/ExecutionEngine/TargetSelect.cpp | 7 - llvm/lib/MC/MCDisassembler/Disassembler.cpp | 3 +- llvm/lib/MC/MCDisassembler/MCDisassembler.cpp | 7 +- llvm/lib/Support/CrashRecoveryContext.cpp | 65 +- llvm/lib/Support/Unix/Signals.inc | 16 + llvm/lib/Support/Windows/Signals.inc | 57 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 1 - .../AArch64/Disassembler/AArch64Disassembler.h | 3 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 1 - .../AMDGPU/Disassembler/AMDGPUDisassembler.h | 2 +- .../Target/ARC/Disassembler/ARCDisassembler.cpp | 2 - .../Target/ARM/Disassembler/ARMDisassembler.cpp | 20 +- .../Target/AVR/Disassembler/AVRDisassembler.cpp | 2 - .../Target/BPF/Disassembler/BPFDisassembler.cpp | 2 - .../Hexagon/Disassembler/HexagonDisassembler.cpp | 15 +- .../Lanai/Disassembler/LanaiDisassembler.cpp | 7 +- .../Target/Lanai/Disassembler/LanaiDisassembler.h | 3 +- .../MSP430/Disassembler/MSP430Disassembler.cpp | 14 +- .../Target/Mips/Disassembler/MipsDisassembler.cpp | 2 - .../PowerPC/Disassembler/PPCDisassembler.cpp | 4 +- .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 - .../Sparc/Disassembler/SparcDisassembler.cpp | 2 - .../SystemZ/Disassembler/SystemZDisassembler.cpp | 2 - .../Disassembler/WebAssemblyDisassembler.cpp | 6 +- llvm/lib/Target/X86/Disassembler/CMakeLists.txt | 1 - .../Target/X86/Disassembler/X86Disassembler.cpp | 1666 ++++++++++++++++- .../X86/Disassembler/X86DisassemblerDecoder.cpp | 1920 -------------------- .../X86/Disassembler/X86DisassemblerDecoder.h | 69 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 + llvm/lib/Target/X86/X86ISelLowering.cpp | 25 +- llvm/lib/Target/X86/X86InstrAVX512.td | 60 - llvm/lib/Target/X86/X86InstrSSE.td | 7 - .../XCore/Disassembler/XCoreDisassembler.cpp | 8 +- .../test/Analysis/ScalarEvolution/range_nw_flag.ll | 8 +- llvm/test/CodeGen/AMDGPU/shl.ll | 1717 ++++++++++++++--- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 196 +- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 246 +-- llvm/test/CodeGen/X86/avx-unpack.ll | 8 +- .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 98 +- llvm/test/CodeGen/X86/subvector-broadcast.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 129 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 26 +- llvm/test/ExecutionEngine/OrcLazy/printargv.ll | 81 + llvm/tools/lli/lli.cpp | 10 +- llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp | 2 +- llvm/tools/llvm-exegesis/lib/Analysis.cpp | 2 +- llvm/tools/llvm-mc/Disassembler.cpp | 3 +- llvm/tools/llvm-objdump/MachODump.cpp | 12 +- llvm/tools/llvm-objdump/llvm-objdump.cpp | 11 +- llvm/tools/sancov/sancov.cpp | 2 +- llvm/unittests/Support/CrashRecoveryTest.cpp | 30 + llvm/utils/TableGen/X86DisassemblerTables.cpp | 88 +- .../llvm/lib/Target/X86/Disassembler/BUILD.gn | 1 - 69 files changed, 4073 insertions(+), 3396 deletions(-) delete mode 100644 llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp create mode 100644 llvm/test/ExecutionEngine/OrcLazy/printargv.ll