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from 1a07bc9cda7 Simplify (_Float16) sqrtf((float) a) to .SQRT(a) when a is [...] new 149e217033f RISC-V: Minimal support of bitmanip extension new 283b1707f23 RISC-V: Implement instruction patterns for ZBA extension. new 04a9b554ba1 RISC-V: Cost model for zba extension. new e596a283e54 RISC-V: Implement instruction patterns for ZBB extension. new 3329d892eb6 RISC-V: Cost model for zbb extension. new 26d2818bb73 RISC-V: Use li and rori to load constants. new 4e1e0d79ecb RISC-V: Implement instruction patterns for ZBS extension. new 77b84fb0a8e RISC-V: Cost model for ZBS extension.

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Summary of changes: gcc/common/config/riscv/riscv-common.c | 10 + gcc/config/riscv/bitmanip.md | 342 +++++++++++++++++++++ gcc/config/riscv/predicates.md | 22 ++ gcc/config/riscv/riscv-opts.h | 10 + gcc/config/riscv/riscv.c | 221 ++++++++++++- gcc/config/riscv/riscv.h | 8 + gcc/config/riscv/riscv.md | 33 +- gcc/config/riscv/riscv.opt | 3 + gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 + gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c | 19 ++ gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c | 19 ++ gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c | 31 ++ gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 + gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 + .../gcc.target/riscv/zbb-andn-orn-xnor-01.c | 21 ++ .../gcc.target/riscv/zbb-andn-orn-xnor-02.c | 21 ++ gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 +++ gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 31 ++ gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c | 16 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c | 16 + gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 17 + gcc/testsuite/gcc.target/riscv/zbbw.c | 25 ++ gcc/testsuite/gcc.target/riscv/zbs-bclr.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-binv.c | 20 ++ gcc/testsuite/gcc.target/riscv/zbs-bset.c | 41 +++ 26 files changed, 1024 insertions(+), 10 deletions(-) create mode 100644 gcc/config/riscv/bitmanip.md create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-andn-orn-xnor-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bclr.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bext.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-binv.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bset.c