On Wed, Nov 23, 2016 at 03:12:27PM +0800, Haojian Zhuang wrote:

Only add the skeleton of HiKey platform.

It would be useful to have a quick description of HiKey here, mentioning it is a 96boards CE platform, which SoC it is based on and so.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang haojian.zhuang@linaro.org

---

Chips/Hisilicon/Hi6220/Hi6220.dec | 33 ++ Chips/Hisilicon/Hi6220/Include/Hi6220.h | 75 +++ Platforms/Hisilicon/HiKey/HiKey.dec | 42 ++ Platforms/Hisilicon/HiKey/HiKey.dsc | 503 +++++++++++++++++++++ Platforms/Hisilicon/HiKey/HiKey.fdf | 352 ++++++++++++++ Platforms/Hisilicon/HiKey/Include/ArmPlatform.h | 27 ++ Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c | 160 +++++++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S | 49 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf | 54 +++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c | 210 +++++++++ 10 files changed, 1505 insertions(+) create mode 100644 Chips/Hisilicon/Hi6220/Hi6220.dec create mode 100644 Chips/Hisilicon/Hi6220/Include/Hi6220.h create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dec create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dsc create mode 100644 Platforms/Hisilicon/HiKey/HiKey.fdf create mode 100644 Platforms/Hisilicon/HiKey/Include/ArmPlatform.h create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c

diff --git a/Chips/Hisilicon/Hi6220/Hi6220.dec b/Chips/Hisilicon/Hi6220/Hi6220.dec new file mode 100644 index 0000000..644ea31 --- /dev/null +++ b/Chips/Hisilicon/Hi6220/Hi6220.dec @@ -0,0 +1,33 @@ +# +# Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +# Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved.

It's up to you, but I would say you could bump these to 2016 now that you are contributing. Whichever you choose, keep it consistent throughout.

+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#

+[Defines]

• DEC_SPECIFICATION = 0x00010005

Current .dec specification is 1.25, so these could all be bumped to 0x00010019 throughout.

• PACKAGE_NAME = HiKey
• PACKAGE_GUID = 01be44a1-5ed3-47fc-8ecf-daa83344678c
• PACKAGE_VERSION = 0.1

+################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common]

• Include # Root include for the package

+[Guids.common]

• gHi6220TokenSpaceGuid = { 0x47fc9a0e, 0x1796, 0x4d04, { 0xaf, 0x68, 0x2b, 0xcb, 0x0d, 0x40, 0x84, 0x09} }

diff --git a/Chips/Hisilicon/Hi6220/Include/Hi6220.h b/Chips/Hisilicon/Hi6220/Include/Hi6220.h new file mode 100644 index 0000000..42a6895 --- /dev/null +++ b/Chips/Hisilicon/Hi6220/Include/Hi6220.h @@ -0,0 +1,75 @@ +/** @file +* +* Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +* Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __HI6220_H__ +#define __HI6220_H__

+/*********************************************************************************** +// Platform Memory Map +************************************************************************************/

+// SOC peripherals (UART, I2C, I2S, USB, etc) +#define HI6220_PERIPH_BASE 0xF4000000 +#define HI6220_PERIPH_SZ 0x05800000

+#define PERI_CTRL_BASE 0xF7030000 +#define SC_PERIPH_CTRL4 0x00C

There are tabs in this file, which causes the funky indentation. Tabs are banned by the Tianocore coding style.

I highly recommend emacs "M-x untabify".

+#define CTRL4_FPGA_EXT_PHY_SEL BIT3 +#define CTRL4_PICO_SIDDQ BIT6 +#define CTRL4_PICO_OGDISABLE BIT8 +#define CTRL4_PICO_VBUSVLDEXT BIT10 +#define CTRL4_PICO_VBUSVLDEXTSEL BIT11 +#define CTRL4_OTG_PHY_SEL BIT21

+#define SC_PERIPH_CTRL5 0x010

+#define CTRL5_USBOTG_RES_SEL BIT3 +#define CTRL5_PICOPHY_ACAENB BIT4 +#define CTRL5_PICOPHY_BC_MODE BIT5 +#define CTRL5_PICOPHY_CHRGSEL BIT6 +#define CTRL5_PICOPHY_VDATSRCEND BIT7 +#define CTRL5_PICOPHY_VDATDETENB BIT8 +#define CTRL5_PICOPHY_DCDENB BIT9 +#define CTRL5_PICOPHY_IDDIG BIT10

+#define SC_PERIPH_CTRL8 0x018 +#define SC_PERIPH_CLKEN0 0x200 +#define SC_PERIPH_CLKDIS0 0x204 +#define SC_PERIPH_CLKSTAT0 0x208

+#define SC_PERIPH_RSTEN0 0x300 +#define SC_PERIPH_RSTDIS0 0x304 +#define SC_PERIPH_RSTSTAT0 0x308

+#define RST0_USBOTG_BUS BIT4 +#define RST0_POR_PICOPHY BIT5 +#define RST0_USBOTG BIT6 +#define RST0_USBOTG_32K BIT7

+#define EYE_PATTERN_PARA 0x7053348c

+#define MDDRC_AXI_BASE 0xF7120000 +#define AXI_REGION_MAP_OFFSET(x) ( 0x100 + ( x ) * 0x10 )

+#define AO_CTRL_BASE 0xF7800000 +#define SC_PW_MTCMOS_EN0 0x830 +#define SC_PW_MTCMOS_DIS0 0x834 +#define SC_PW_MTCMOS_STAT0 0x838 +#define SC_PW_MTCMOS_ACK_STAT0 0x83c +#define PW_EN0_G3D (1 << 1)

+#define PMUSSI_BASE 0xF8000000

+#endif /* __HI6220_H__ */ diff --git a/Platforms/Hisilicon/HiKey/HiKey.dec b/Platforms/Hisilicon/HiKey/HiKey.dec new file mode 100644 index 0000000..70f441f --- /dev/null +++ b/Platforms/Hisilicon/HiKey/HiKey.dec @@ -0,0 +1,42 @@ +# +# Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +# Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#

+[Defines]

• DEC_SPECIFICATION = 0x00010005
• PACKAGE_NAME = HiKey
• PACKAGE_GUID = d6db414d-ea67-4312-94d5-9c9e5b224d25
• PACKAGE_VERSION = 0.1

+################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common]

• Include # Root include for the package

+[Guids.common]

• gArmPL061GpioGuid = { 0x5c1997d7, 0x8d45, 0x4f21, { 0xaf, 0x3c, 0x22, 0x06, 0xb8, 0xed, 0x8b, 0xec } }
• gDwUsbDeviceGuid = { 0x72d78ea6, 0x4dee, 0x11e3, { 0x81, 0x00, 0xf3, 0x84, 0x2a, 0x48, 0xd0, 0xa0 } }
• gFaultTolerantWriteGuid = { 0xfe5cea76, 0x4f72, 0x49e8, { 0x98, 0x6f, 0x2c, 0xd8, 0x99, 0xdf, 0xfe, 0x5d } }

I am a little bit confused by these, which appear to be explicit mappings for FILE_GUIDs for various components. I think these are probably not needed, but let's see what you do with them.

• gHiKeyTokenSpaceGuid = { 0x91148425, 0xcdd2, 0x4830, { 0x8b, 0xd0, 0xc6, 0x1c, 0x6d, 0xea, 0x36, 0x21 } }
• gHiKeyVariableGuid = { 0x66b8d063, 0x1daa, 0x4c60, { 0xb9, 0xf2, 0x55, 0x0d, 0x7e, 0xe1, 0x2f, 0x38 } }

+[PcdsFixedAtBuild.common]

• gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L""|VOID*|0x00000001
• gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|L""|VOID*|0x00000002
• gHiKeyTokenSpaceGuid.PcdBootImagePath|L""|VOID*|0x00000003

diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc new file mode 100644 index 0000000..40bd728 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -0,0 +1,503 @@ +# +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#

+################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines]

• PLATFORM_NAME = HiKey
• PLATFORM_GUID = 8edf1480-da5c-4857-bc02-7530bd8e7b7a
• PLATFORM_VERSION = 0.2
• DSC_SPECIFICATION = 0x00010005
• OUTPUT_DIRECTORY = Build/HiKey
• SUPPORTED_ARCHITECTURES = AARCH64
• BUILD_TARGETS = DEBUG|RELEASE
• SKUID_IDENTIFIER = DEFAULT
• FLASH_DEFINITION = OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.fdf

+[LibraryClasses.common] +!if $(TARGET) == RELEASE

• DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!else

• DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!endif

• DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
• ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
• ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
• ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
• ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
• ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
• ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
• ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
• ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
• ArmPlatformLib|OpenPlatformPkg/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf
• ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
• ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf
• BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
• BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
• CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
• DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
• CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
• CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
• DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
• DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
• DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
• EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
• MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
• SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
• FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
• UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
• PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
• CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
• # RunAxf support via Dynamic Shell Command protocol
• # It uses the Shell libraries.
• ArmShellCmdRunAxfLib|ArmPlatformPkg/Library/ArmShellCmdRunAxf/ArmShellCmdRunAxf.inf
• ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
• FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
• SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
• # UiApp dependencies
• ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
• FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
• DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
• HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
• IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
• HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
• UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
• TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
• UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
• UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
• UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
• PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
• SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
• RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
• NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
• #
• # Assume everything is fixed at build
• #
• PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
• PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
• PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
• PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
• PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
• PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
• UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
• UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
• UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
• UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
• # USB Requirements
• UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
• DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
• UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
• # Network Libraries
• UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
• NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
• DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
• IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
• UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf

+[LibraryClasses.AARCH64]

• ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf

+[LibraryClasses.common.SEC]

• PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
• ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
• LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
• MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
• HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
• PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
• PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
• PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
• MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
• ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
• DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf

+[LibraryClasses.common.DXE_CORE]

• DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
• DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
• ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
• HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
• MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
• ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf

+[LibraryClasses.common.UEFI_DRIVER]

• ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf

+[LibraryClasses.common.DXE_DRIVER]

• DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
• MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
• ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
• SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf

+[LibraryClasses.common.DXE_RUNTIME_DRIVER]

• CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
• HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
• MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
• ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf

+[BuildOptions]

• GCC:*_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/MdeModulePkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Include -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include -I$(WORKSPACE)/OpenPlatformPkg/Platforms/Hisilicon/HiKey/Include

Surely we don't need an explicit statement for -I$(WORKSPACE)/MdeModulePkg/Include, and I don't believe there exists a -I$(WORKSPACE)/OpenPlatformPkg/Include?

+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]

• GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000

Is it valid to build this port for AArch32?

• GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000

+################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################

+[PcdsFeatureFlag.common]

• gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
• gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
• gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
• gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
• #
• # Control what commands are supported from the UI
• # Turn these on and off to add features or save size
• #
• gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
• gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
• gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
• # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
• gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
• gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
• gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
• ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
• # It could be set FALSE to save size.
• gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
• gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE

+[PcdsFixedAtBuild.common]

• gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
• gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
• gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
• gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
• gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
• gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
• gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
• gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
• # DEBUG_ASSERT_ENABLED 0x01
• # DEBUG_PRINT_ENABLED 0x02
• # DEBUG_CODE_ENABLED 0x04
• # CLEAR_MEMORY_ENABLED 0x08
• # ASSERT_BREAKPOINT_ENABLED 0x10
• # ASSERT_DEADLOOP_ENABLED 0x20

+!if $(TARGET) == RELEASE

• gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21

+!else

• gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f

+!endif

• # DEBUG_INIT 0x00000001 // Initialization
• # DEBUG_WARN 0x00000002 // Warnings
• # DEBUG_LOAD 0x00000004 // Load events
• # DEBUG_FS 0x00000008 // EFI File system
• # DEBUG_POOL 0x00000010 // Alloc & Free's
• # DEBUG_PAGE 0x00000020 // Alloc & Free's
• # DEBUG_INFO 0x00000040 // Verbose
• # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
• # DEBUG_VARIABLE 0x00000100 // Variable
• # DEBUG_BM 0x00000400 // Boot Manager
• # DEBUG_BLKIO 0x00001000 // BlkIo Driver
• # DEBUG_NET 0x00004000 // SNI Driver
• # DEBUG_UNDI 0x00010000 // UNDI Driver
• # DEBUG_LOADFILE 0x00020000 // UNDI Driver

There have been some typo fixes in the file you used as a template for this, it could be worth copying this comment across again.

• # DEBUG_EVENT 0x00080000 // Event messages
• # DEBUG_GCD 0x00100000 // Global Coherency Database changes
• # DEBUG_CACHE 0x00200000 // Memory range cachability changes
• # DEBUG_ERROR 0x80000000 // Error
• gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
• gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
• #
• # Optional feature to help prevent EFI memory map fragments
• # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
• # Values are in EFI Pages (4K). DXE Core will make sure that
• # at least this much of each type of memory can be allocated
• # from a single memory range. This way you only end up with
• # maximum of two fragements for each type in the memory map
• # (the memory used, and the free memory that was prereserved
• # but not used).
• #
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
• gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
• gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
• gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
• gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
• gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
• gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"hikey"
• gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
• gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey"
• #
• # NV Storage PCDs.
• #
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x30000000
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x30010000
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x30020000
• gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
• # System Memory (1GB)
• gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
• gArmTokenSpaceGuid.PcdSystemMemorySize|0x3E000000
• # HiKey Dual-Cluster profile
• gArmPlatformTokenSpaceGuid.PcdCoreCount|8
• gArmPlatformTokenSpaceGuid.PcdClusterCount|2
• gArmTokenSpaceGuid.PcdVFPEnabled|1
• #
• # ARM Pcds
• #
• gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
• #
• # ARM PrimeCell
• #
• ## PL011 - Serial Terminal
• DEFINE SERIAL_BASE = 0xF7113000 # UART3
• gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
• gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
• gArmPlatformTokenSpaceGuid.PL011UartInteger|10
• gArmPlatformTokenSpaceGuid.PL011UartFractional|26
• ## PL031 RealTimeClock
• gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
• #
• # ARM General Interrupt Controller
• #
• gArmTokenSpaceGuid.PcdGicDistributorBase|0xF6801000
• gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF6802000
• # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
• gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
• gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
• gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
• # GUID of the UEFI Shell
• gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
• # GUID of the UI app
• gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
• gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
• #
• # ARM Architectural Timer Frequency
• #
• gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|1200000
• gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
• #
• # Fastboot
• #
• gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1
• gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d

+[PcdsDynamicDefault.common]

• #
• # The size of a dynamic PCD of the (VOID*) type can not be increased at run
• # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128
• # character "empty" string, to allow to be able to set FDT text device paths
• # up to 128 characters long.
• #
• gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" "

+################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common]

• #
• # PEI Phase modules
• #
• ArmPlatformPkg/PrePi/PeiMPCore.inf
• #
• # DXE
• #
• MdeModulePkg/Core/Dxe/DxeMain.inf {

• <LibraryClasses>

•  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
  

•  NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
  

• }
• #
• # Architectural Protocols
• #
• ArmPkg/Drivers/CpuDxe/CpuDxe.inf
• MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
• MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
• MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
• EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
• EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
• EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
• EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
• MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
• MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
• MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
• MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
• MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
• MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
• ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
• ArmPkg/Drivers/TimerDxe/TimerDxe.inf
• MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
• #
• # GPIO
• #
• ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
• #
• # MMC/SD
• #
• EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
• #
• # USB Host Support
• #
• MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
• #
• # USB Mass Storage Support
• #
• MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
• #
• # USB Peripheral Support
• #
• EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
• #
• # Fastboot
• #
• EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf {

• <LibraryClasses>

•  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
  

• }
• #
• # UEFI Network Stack
• #
• MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
• MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
• MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
• MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
• MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
• MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
• MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
• MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
• MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
• #
• # AX88772 Ethernet Driver
• #
• OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
• #
• # FAT filesystem + GPT/MBR partitioning
• #
• MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
• MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
• MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
• #
• # Bds
• #
• MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
• MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
• MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
• MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
• MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
• MdeModulePkg/Application/UiApp/UiApp.inf {

• <LibraryClasses>

•  NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
  

•  NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
  

•  NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
  

• }
• ShellPkg/Application/Shell/Shell.inf {

• <LibraryClasses>

•  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
  

•  NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
  

•  NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
  

•  HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
  

•  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
  

•  BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
  

• <PcdsFixedAtBuild>

•  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
  

•  gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
  

•  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
  

• }
• # Legacy Linux Loader
• ArmPkg/Application/LinuxLoader/LinuxLoader.inf {

• <LibraryClasses>

•  BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
  

• }

diff --git a/Platforms/Hisilicon/HiKey/HiKey.fdf b/Platforms/Hisilicon/HiKey/HiKey.fdf new file mode 100644 index 0000000..8f292a0 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/HiKey.fdf @@ -0,0 +1,352 @@ +# +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#

+################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################

+[FD.BL33_AP_UEFI] +BaseAddress = 0x35000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1

+# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0xF0

+################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################

+0x00000000|0x000F0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT

+################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################

+[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE

• INF MdeModulePkg/Core/Dxe/DxeMain.inf
• #
• # PI DXE Drivers producing Architectural Protocols (EFI Services)
• #
• INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
• INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
• INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
• INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
• INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
• INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
• INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
• INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
• #
• # Multiple Console IO support
• #
• INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
• INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
• INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
• INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
• INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
• INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
• #
• # GPIO
• #
• INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
• #
• # Multimedia Card Interface
• #
• INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
• #
• # USB Host Support
• #
• INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
• #
• # USB Mass Storage Support
• #
• INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
• #
• # USB Peripheral Support
• #
• INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
• #
• # Fastboot
• #
• INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
• #
• # UEFI Network Stack
• #
• INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
• INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
• INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
• INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
• INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
• INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
• INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
• INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
• INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
• #
• # AX88772 Ethernet Driver for Apple Ethernet Adapter
• #
• INF OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
• #
• # FAT filesystem + GPT/MBR partitioning
• #
• INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
• INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
• INF FatBinPkg/EnhancedFatDxe/Fat.inf
• INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
• INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
• INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
• INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
• #
• # UEFI applications
• #
• INF ShellPkg/Application/Shell/Shell.inf
• #
• # Bds
• #
• INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
• INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
• INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
• INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
• INF MdeModulePkg/Application/UiApp/UiApp.inf
• #
• # Legacy Linux Loader
• #
• INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf

+[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE

• INF ArmPlatformPkg/PrePi/PeiMPCore.inf
• FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
• SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

•  SECTION FV_IMAGE = FVMAIN
  

• }
• }

+################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################

+############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################

+# +# These SEC rules are used for ArmPlatformPkg/PrePi module. +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint +# +[Rule.ARM.SEC]

• FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
• TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• }

+[Rule.AARCH64.SEC]

• FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
• TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
• }

+# A shim specific rule is required to ensure the alignment is 4K. +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32) +[Rule.ARM.SEC.SHIM]

• FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
• TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
• }

+[Rule.Common.PEI_CORE]

• FILE PEI_CORE = $(NAMED_GUID) {
• TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
• UI STRING ="$(MODULE_NAME)" Optional
• }

+[Rule.Common.PEIM]

• FILE PEIM = $(NAMED_GUID) {

• PEI_DEPEX PEI_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
  

• TE       TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
  

• UI       STRING="$(MODULE_NAME)" Optional
  

• }

+[Rule.Common.PEIM.TIANOCOMPRESSED]

• FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
• PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
• GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {

•  PE32      PE32                    $(INF_OUTPUT)/$(MODULE_NAME).efi
  

•  UI        STRING="$(MODULE_NAME)" Optional
  

• }
• }

+[Rule.Common.DXE_CORE]

• FILE DXE_CORE = $(NAMED_GUID) {
• PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• UI STRING="$(MODULE_NAME)" Optional
• }

+[Rule.Common.UEFI_DRIVER]

• FILE DRIVER = $(NAMED_GUID) {
• DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
• PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• UI STRING="$(MODULE_NAME)" Optional
• }

+[Rule.Common.DXE_DRIVER]

• FILE DRIVER = $(NAMED_GUID) {
• DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
• PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• UI STRING="$(MODULE_NAME)" Optional
• }

+[Rule.Common.DXE_DRIVER.BINARY]

• FILE DRIVER = $(NAMED_GUID) {
• DXE_DEPEX DXE_DEPEX Optional |.depex
• PE32 PE32 |.efi
• UI STRING="$(MODULE_NAME)" Optional
• }

+[Rule.Common.DXE_RUNTIME_DRIVER]

• FILE DRIVER = $(NAMED_GUID) {
• DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
• PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• UI STRING="$(MODULE_NAME)" Optional
• }

+[Rule.Common.UEFI_APPLICATION]

• FILE APPLICATION = $(NAMED_GUID) {
• UI STRING ="$(MODULE_NAME)" Optional
• PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
• }

+[Rule.Common.UEFI_DRIVER.BINARY]

• FILE DRIVER = $(NAMED_GUID) {
• DXE_DEPEX DXE_DEPEX Optional |.depex
• PE32 PE32 |.efi
• UI STRING="$(MODULE_NAME)" Optional
• VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
• }

+[Rule.Common.UEFI_APPLICATION.BINARY]

• FILE APPLICATION = $(NAMED_GUID) {
• PE32 PE32 |.efi
• UI STRING="$(MODULE_NAME)" Optional
• VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
• }

+[Rule.Common.USER_DEFINED.ACPITABLE]

• FILE FREEFORM = $(NAMED_GUID) {
• RAW ACPI |.acpi
• RAW ASL |.aml
• }

diff --git a/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h b/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h new file mode 100644 index 0000000..ae2367e --- /dev/null +++ b/Platforms/Hisilicon/HiKey/Include/ArmPlatform.h @@ -0,0 +1,27 @@ +/** @file +* +* Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +* Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __PLATFORM_H__ +#define __PLATFORM_H__

+// +// We don't care about this value, but the PL031 driver depends on the macro +// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet() +// function, which just returns EFI_UNSUPPORTED. +// +// +#define SYS_CFG_RTC 0

+#endif /* __PLATFORM_H__ */ diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c new file mode 100644 index 0000000..8c4bd77 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c @@ -0,0 +1,160 @@ +/** @file +* +* Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +* Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h>

Could you sort the include files alphabetically, please?

+#include <Ppi/ArmMpCoreInfo.h>

+#include <Hi6220.h>

+ARM_CORE_INFO mHiKeyInfoTable[] = {

• {
• // Cluster 0, Core 0
• 0x0, 0x0,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 0, Core 1
• 0x0, 0x1,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 0, Core 2
• 0x0, 0x2,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 0, Core 3
• 0x0, 0x3,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 1, Core 0
• 0x1, 0x0,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 1, Core 1
• 0x1, 0x1,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 1, Core 2
• 0x1, 0x2,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• },
• {
• // Cluster 1, Core 3
• 0x1, 0x3,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (UINT64)0xFFFFFFFF
• }

+};

+/**

• Return the current Boot Mode
• This function returns the boot reason on the platform
• @return Return the current Boot Mode of the platform

+**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode (

• VOID
• )

+{

• return BOOT_WITH_FULL_CONFIGURATION;

+}

+/**

• Initialize controllers that must setup in the normal world
• This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
• in the PEI phase.

+**/ +RETURN_STATUS +ArmPlatformInitialize (

• IN UINTN MpId
• )

+{

• return RETURN_SUCCESS;

+}

+/**

• Initialize the system (or sometimes called permanent) memory
• This memory is generally represented by the DRAM.

+**/ +VOID +ArmPlatformInitializeSystemMemory (

• VOID
• )

+{ +}

+EFI_STATUS +PrePeiCoreGetMpCoreInfo (

• OUT UINTN *CoreCount,
• OUT ARM_CORE_INFO **ArmCoreTable
• )

+{

• // Only support one cluster
• *CoreCount = sizeof(mHiKeyInfoTable) / sizeof(ARM_CORE_INFO);
• *ArmCoreTable = mHiKeyInfoTable;
• return EFI_SUCCESS;

+}

+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };

+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {

• {
• EFI_PEI_PPI_DESCRIPTOR_PPI,
• &mArmMpCoreInfoPpiGuid,
• &mMpCoreInfoPpi
• }

+};

+VOID +ArmPlatformGetPlatformPpiList (

• OUT UINTN *PpiListSize,
• OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
• )

+{

• *PpiListSize = sizeof(gPlatformPpiTable);
• *PpiList = gPlatformPpiTable;

+} diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S new file mode 100644 index 0000000..dfaf4a6 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S @@ -0,0 +1,49 @@ +# +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#

+#include <AsmMacroIoLibV8.h> +#include <Library/ArmLib.h>

+ASM_FUNC(ArmPlatformPeiBootAction)

• ret

+//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition)

• and x1, x0, #ARM_CORE_MASK
• and x0, x0, #ARM_CLUSTER_MASK
• add x0, x1, x0, LSR #6
• ret

+//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)

• MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
• ret

+//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore)

• MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
• and x0, x0, x1
• MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
• cmp w0, w1
• cset x0, eq
• ret

diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf new file mode 100644 index 0000000..287fdb2 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf @@ -0,0 +1,54 @@ +# +# Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +# Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +#

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = HiKeyLib
• FILE_GUID = 1f6c5192-f35c-462d-877c-8ee3227fff01
• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = ArmPlatformLib

+[Packages]

• MdePkg/MdePkg.dec
• MdeModulePkg/MdeModulePkg.dec
• EmbeddedPkg/EmbeddedPkg.dec
• ArmPkg/ArmPkg.dec
• ArmPlatformPkg/ArmPlatformPkg.dec
• OpenPlatformPkg/Chips/Hisilicon/Hi6220/Hi6220.dec
• OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dec

+[LibraryClasses]

• IoLib
• ArmLib
• HobLib
• MemoryAllocationLib
• SerialPortLib

+[Sources.common]

• HiKey.c
• HiKeyMem.c

+[Sources.AARCH64]

• HiKeyHelper.S

+[FeaturePcd]

• gEmbeddedTokenSpaceGuid.PcdCacheEnable

+[FixedPcd]

• gArmTokenSpaceGuid.PcdSystemMemoryBase
• gArmTokenSpaceGuid.PcdSystemMemorySize
• gArmTokenSpaceGuid.PcdFvBaseAddress
• gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
• gArmTokenSpaceGuid.PcdArmPrimaryCore

Could you sort the Packages, LibraryClasses and FixedPcd entries alphabetically under each section?

diff --git a/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c new file mode 100644 index 0000000..2d118e0 --- /dev/null +++ b/Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c @@ -0,0 +1,210 @@ +/** @file +* +* Copyright (c) 2014-2015, Linaro Limited. All rights reserved. +* Copyright (c) 2014-2015, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/HobLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h>

Sort alphabetically, please.

+#include <Hi6220.h>

+// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12

+// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

+#define HIKEY_EXTRA_SYSTEM_MEMORY_BASE 0x40000000 +#define HIKEY_EXTRA_SYSTEM_MEMORY_SIZE 0x40000000

+STATIC struct HiKeyReservedMemory {

• EFI_PHYSICAL_ADDRESS Offset;
• EFI_PHYSICAL_ADDRESS Size;

+} HiKeyReservedMemoryBuffer [] = {

• { 0x05E00000, 0x00100000 }, // MCU
• { 0x05F01000, 0x00001000 }, // ADB REBOOT "REASON"
• { 0x06DFF000, 0x00001000 }, // MAILBOX
• { 0x0740F000, 0x00001000 }, // MAILBOX
• { 0x21F00000, 0x00100000 }, // PSTORE/RAMOOPS
• { 0x3E000000, 0x02000000 } // TEE OS

+};

+STATIC +UINT64 +EFIAPI +HiKeyInitMemorySize (

• IN VOID
• )

+{

• UINT32 Count, Data, MemorySize;
• Count = 0;
• while (MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP_OFFSET (Count)) != 0) {
• Count++;
• }
• Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP_OFFSET (Count - 1));
• MemorySize = 16 << ((Data >> 8) & 0x7);
• MemorySize += Data << 24;
• return (UINT64) (MemorySize << 20);

+}

+/**

• Return the Virtual Memory Map of your platform
• This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
• @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-

•                                Virtual Memory mapping. This array must be ended by a zero-filled
  

•                                entry
  

+**/ +VOID +ArmPlatformGetVirtualMemoryMap (

• IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
• )

+{

• ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
• UINTN Index = 0, Count, ReservedTop;
• ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
• EFI_PEI_HOB_POINTERS NextHob;
• EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
• UINT64 ResourceLength;
• EFI_PHYSICAL_ADDRESS ResourceTop;
• UINT64 MemorySize, AdditionalMemorySize;
• MemorySize = HiKeyInitMemorySize ();
• ResourceAttributes = (

•  EFI_RESOURCE_ATTRIBUTE_PRESENT |
  

•  EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  

•  EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  

•  EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  

•  EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  

•  EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  

•  EFI_RESOURCE_ATTRIBUTE_TESTED
  

• );
• // Create initial Base Hob for system memory.
• BuildResourceDescriptorHob (

•  EFI_RESOURCE_SYSTEM_MEMORY,
  

•  ResourceAttributes,
  

•  PcdGet64 (PcdSystemMemoryBase),
  

•  PcdGet64 (PcdSystemMemorySize)
  

• );
• NextHob.Raw = GetHobList ();
• Count = sizeof (HiKeyReservedMemoryBuffer) / sizeof (struct HiKeyReservedMemory);
• while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL)
• {

That { should come at the end of the line before.

• if (Index >= Count)

•  break;
  

• if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&

•    (HiKeyReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) &&
  

•    ((HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size) <=
  

•     NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength))
  

• {

As should this one.

•  ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
  

•  ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
  

•  ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
  

•  ReservedTop = HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size;
  

•  // Create the System Memory HOB for the reserved buffer
  

•  BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
  

•                              EFI_RESOURCE_ATTRIBUTE_PRESENT,
  

•                              HiKeyReservedMemoryBuffer[Index].Offset,
  

•                              HiKeyReservedMemoryBuffer[Index].Size);
  

•  // Update the HOB
  

•  NextHob.ResourceDescriptor->ResourceLength = HiKeyReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart;
  

•  // If there is some memory available on the top of the reserved memory then create a HOB
  

•  if (ReservedTop < ResourceTop)
  

•  {
  

And this one.

•    BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
  

•                                ResourceAttributes,
  

•                                ReservedTop,
  

•                                ResourceTop - ReservedTop);
  

•  }
  

•  Index++;
  

• }
• NextHob.Raw = GET_NEXT_HOB (NextHob);
• }
• AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
• if (AdditionalMemorySize >= SIZE_1GB) {

Like that one :)

Regards,

Leif

• // Declared the additional memory
• ResourceAttributes =

•    EFI_RESOURCE_ATTRIBUTE_PRESENT |
  

•    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  

•    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  

•    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  

•    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  

•    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  

•    EFI_RESOURCE_ATTRIBUTE_TESTED;
  

• BuildResourceDescriptorHob (

•  EFI_RESOURCE_SYSTEM_MEMORY,
  

•  ResourceAttributes,
  

•  HIKEY_EXTRA_SYSTEM_MEMORY_BASE,
  

•  HIKEY_EXTRA_SYSTEM_MEMORY_SIZE);
  

• }
• ASSERT (VirtualMemoryMap != NULL);
• VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
• if (VirtualMemoryTable == NULL) {

•  return;
  

• }
• if (FeaturePcdGet(PcdCacheEnable) == TRUE) {

•  CacheAttributes = DDR_ATTRIBUTES_CACHED;
  

• } else {

•  CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
  

• }
• Index = 0;
• // Hi6220 SOC peripherals
• VirtualMemoryTable[Index].PhysicalBase = HI6220_PERIPH_BASE;
• VirtualMemoryTable[Index].VirtualBase = HI6220_PERIPH_BASE;
• VirtualMemoryTable[Index].Length = HI6220_PERIPH_SZ;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
• // DDR - predefined 1GB size
• VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
• VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
• VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // If DDR capacity is 2GB size, append a new entry to fill the gap.
• if (AdditionalMemorySize >= SIZE_1GB) {
• VirtualMemoryTable[++Index].PhysicalBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
• VirtualMemoryTable[Index].VirtualBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE;
• VirtualMemoryTable[Index].Length = HIKEY_EXTRA_SYSTEM_MEMORY_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• }
• // End of Table
• VirtualMemoryTable[++Index].PhysicalBase = 0;
• VirtualMemoryTable[Index].VirtualBase = 0;
• VirtualMemoryTable[Index].Length = 0;
• VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
• ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
• *VirtualMemoryMap = VirtualMemoryTable;

+}

2.7.4

On 23 November 2016 at 07:12, Haojian Zhuang haojian.zhuang@linaro.org wrote:

Support designware emmc controller.

Can we use the same driver for the MMC and the SD?

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang haojian.zhuang@linaro.org

---

Drivers/Mmc/DwEmmcDxe/DwEmmc.h | 128 +++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c | 651 ++++++++++++++++++++++++++++++++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec | 42 +++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf | 55 +++ 4 files changed, 876 insertions(+) create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmc.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf

diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmc.h b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h new file mode 100644 index 0000000..999b584 --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h @@ -0,0 +1,128 @@ +/** @file +* +* Copyright (c) 2014, Linaro Limited. All rights reserved. +* Copyright (c) 2014, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __DWEMMC_H__ +#define __DWEMMC_H__

+#include <Protocol/EmbeddedGpio.h>

+// DW MMC Registers +#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000) +#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004) +#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008) +#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c) +#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010) +#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014) +#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018) +#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c) +#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020) +#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024) +#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028) +#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c) +#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030) +#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034) +#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038) +#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c) +#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044) +#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048) +#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c) +#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064) +#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074) +#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080) +#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088) +#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c) +#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090) +#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094) +#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098) +#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)

+#define CMD_UPDATE_CLK 0x80202000 +#define CMD_START_BIT (1 << 31)

+#define MMC_8BIT_MODE (1 << 16)

+#define BIT_CMD_RESPONSE_EXPECT (1 << 6) +#define BIT_CMD_LONG_RESPONSE (1 << 7) +#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) +#define BIT_CMD_DATA_EXPECTED (1 << 9) +#define BIT_CMD_READ (0 << 10) +#define BIT_CMD_WRITE (1 << 10) +#define BIT_CMD_BLOCK_TRANSFER (0 << 11) +#define BIT_CMD_STREAM_TRANSFER (1 << 11) +#define BIT_CMD_SEND_AUTO_STOP (1 << 12) +#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) +#define BIT_CMD_STOP_ABORT_CMD (1 << 14) +#define BIT_CMD_SEND_INIT (1 << 15) +#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) +#define BIT_CMD_READ_CEATA_DEVICE (1 << 22) +#define BIT_CMD_CCS_EXPECTED (1 << 23) +#define BIT_CMD_ENABLE_BOOT (1 << 24) +#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) +#define BIT_CMD_DISABLE_BOOT (1 << 26) +#define BIT_CMD_MANDATORY_BOOT (0 << 27) +#define BIT_CMD_ALTERNATE_BOOT (1 << 27) +#define BIT_CMD_VOLT_SWITCH (1 << 28) +#define BIT_CMD_USE_HOLD_REG (1 << 29) +#define BIT_CMD_START (1 << 31)

+#define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */ +#define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */ +#define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */ +#define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ +#define DWEMMC_INT_DRT (1 << 9) /* Data timeout */ +#define DWEMMC_INT_RTO (1 << 8) /* Response timeout */ +#define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */ +#define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */ +#define DWEMMC_INT_RXDR (1 << 5) +#define DWEMMC_INT_TXDR (1 << 4) +#define DWEMMC_INT_DTO (1 << 3) /* Data trans over */ +#define DWEMMC_INT_CMD_DONE (1 << 2) +#define DWEMMC_INT_RE (1 << 1)

+#define DWEMMC_IDMAC_DES0_DIC (1 << 1) +#define DWEMMC_IDMAC_DES0_LD (1 << 2) +#define DWEMMC_IDMAC_DES0_FS (1 << 3) +#define DWEMMC_IDMAC_DES0_CH (1 << 4) +#define DWEMMC_IDMAC_DES0_ER (1 << 5) +#define DWEMMC_IDMAC_DES0_CES (1 << 30) +#define DWEMMC_IDMAC_DES0_OWN (1 << 31) +#define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff) +#define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) +#define DWEMMC_IDMAC_SWRESET (1 << 0) +#define DWEMMC_IDMAC_FB (1 << 1) +#define DWEMMC_IDMAC_ENABLE (1 << 7)

+#define EMMC_FIX_RCA 6

+/* bits in MMC0_CTRL */ +#define DWEMMC_CTRL_RESET (1 << 0) +#define DWEMMC_CTRL_FIFO_RESET (1 << 1) +#define DWEMMC_CTRL_DMA_RESET (1 << 2) +#define DWEMMC_CTRL_INT_EN (1 << 4) +#define DWEMMC_CTRL_DMA_EN (1 << 5) +#define DWEMMC_CTRL_IDMAC_EN (1 << 25) +#define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)

+#define DWEMMC_STS_DATA_BUSY (1 << 9)

+#define DWEMMC_FIFO_TWMARK(x) (x & 0xfff) +#define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16) +#define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)

+#define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16) +#define DWEMMC_CARD_RD_THR_EN (1 << 0)

+#endif // __DWEMMC_H__ diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c new file mode 100644 index 0000000..cf75e1c --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c @@ -0,0 +1,651 @@ +/** @file

• This file implement the MMC Host Protocol for the DesignWare eMMC.
• Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
• Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#include <Library/BaseMemoryLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/TimerLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Protocol/MmcHost.h>

+#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h>

+#include "DwEmmc.h"

+#define DWEMMC_DESC_PAGE 1 +#define DWEMMC_BLOCK_SIZE 512 +#define DWEMMC_DMA_BUF_SIZE (512 * 8) +#define DWEMMC_MAX_DESC_PAGES 512

+typedef struct {

• UINT32 Des0;
• UINT32 Des1;
• UINT32 Des2;
• UINT32 Des3;

+} DWEMMC_IDMAC_DESCRIPTOR;

+EFI_MMC_HOST_PROTOCOL *gpMmcHost; +DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc; +EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID; +STATIC UINT32 mDwEmmcCommand; +STATIC UINT32 mDwEmmcArgument;

+EFI_STATUS +DwEmmcReadBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• );

+BOOLEAN +DwEmmcIsPowerOn (

• VOID
• )

+{

• return TRUE;

+}

+EFI_STATUS +DwEmmcInitialize (

• VOID
• )

+{

• DEBUG ((EFI_D_BLKIO, "DwEmmcInitialize()"));
• return EFI_SUCCESS;

+}

+BOOLEAN +DwEmmcIsCardPresent (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+BOOLEAN +DwEmmcIsReadOnly (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return FALSE;

+}

+BOOLEAN +DwEmmcIsDmaSupported (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+EFI_STATUS +DwEmmcBuildDevicePath (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
• )

+{

• EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
• NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
• CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
• *DevicePath = NewDevicePathNode;
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcUpdateClock (

• VOID
• )

+{

• UINT32 Data;
• /* CMD_UPDATE_CLK */
• Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |

•    BIT_CMD_START;
  

• MmioWrite32 (DWEMMC_CMD, Data);
• while (1) {
• Data = MmioRead32 (DWEMMC_CMD);
• if (!(Data & CMD_START_BIT)) {

•  break;
  

• }
• Data = MmioRead32 (DWEMMC_RINTSTS);
• if (Data & DWEMMC_INT_HLE) {

•  Print (L"failed to update mmc clock frequency\n");
  

•  return EFI_DEVICE_ERROR;
  

• }
• }
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcSetClock (

• IN UINTN ClockFreq
• )

+{

• UINT32 Divider, Rate, Data;
• EFI_STATUS Status;
• BOOLEAN Found = FALSE;
• for (Divider = 1; Divider < 256; Divider++) {
• Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
• if ((Rate / (2 * Divider)) <= ClockFreq) {

•  Found = TRUE;
  

•  break;
  

• }
• }
• if (Found == FALSE) {
• return EFI_NOT_FOUND;
• }
• // Wait until MMC is idle
• do {
• Data = MmioRead32 (DWEMMC_STATUS);
• } while (Data & DWEMMC_STS_DATA_BUSY);
• // Disable MMC clock first
• MmioWrite32 (DWEMMC_CLKENA, 0);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• MmioWrite32 (DWEMMC_CLKDIV, Divider);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• // Enable MMC clock
• MmioWrite32 (DWEMMC_CLKENA, 1);
• MmioWrite32 (DWEMMC_CLKSRC, 0);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcNotifyState (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_STATE State
• )

+{

• UINT32 Data;
• EFI_STATUS Status;
• switch (State) {
• case MmcInvalidState:
• ASSERT (0);
• break;
• case MmcHwInitializationState:
• MmioWrite32 (DWEMMC_PWREN, 1);
• // If device already turn on then restart it
• Data = DWEMMC_CTRL_RESET_ALL;
• MmioWrite32 (DWEMMC_CTRL, Data);
• do {

•  // Wait until reset operation finished
  

•  Data = MmioRead32 (DWEMMC_CTRL);
  

• } while (Data & DWEMMC_CTRL_RESET_ALL);
• // Setup clock that could not be higher than 400KHz.
• Status = DwEmmcSetClock (400000);
• ASSERT (!EFI_ERROR (Status));
• MicroSecondDelay (100);
• MmioWrite32 (DWEMMC_RINTSTS, ~0);
• MmioWrite32 (DWEMMC_INTMASK, 0);
• MmioWrite32 (DWEMMC_TMOUT, ~0);
• MmioWrite32 (DWEMMC_IDINTEN, 0);
• MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
• MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
• do {

•  Data = MmioRead32 (DWEMMC_BMOD);
  

• } while (Data & DWEMMC_IDMAC_SWRESET);
• break;
• case MmcIdleState:
• break;
• case MmcReadyState:
• break;
• case MmcIdentificationState:
• break;
• case MmcStandByState:
• break;
• case MmcTransferState:
• break;
• case MmcSendingDataState:
• break;
• case MmcReceiveDataState:
• break;
• case MmcProgrammingState:
• break;
• case MmcDisconnectState:
• break;
• default:
• ASSERT (0);
• }
• return EFI_SUCCESS;

+}

+// Need to prepare DMA buffer first before sending commands to MMC card +BOOLEAN +IsPendingReadCommand (

• IN MMC_CMD MmcCmd
• )

+{

• UINTN Mask;
• Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
• if ((MmcCmd & Mask) == Mask) {
• return TRUE;
• }
• return FALSE;

+}

+BOOLEAN +IsPendingWriteCommand (

• IN MMC_CMD MmcCmd
• )

+{

• UINTN Mask;
• Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
• if ((MmcCmd & Mask) == Mask) {
• return TRUE;
• }
• return FALSE;

+}

+EFI_STATUS +SendCommand (

• IN MMC_CMD MmcCmd,
• IN UINT32 Argument
• )

+{

• UINT32 Data, ErrMask;
• // Wait until MMC is idle
• do {
• Data = MmioRead32 (DWEMMC_STATUS);
• } while (Data & DWEMMC_STS_DATA_BUSY);
• MmioWrite32 (DWEMMC_RINTSTS, ~0);
• MmioWrite32 (DWEMMC_CMDARG, Argument);
• MmioWrite32 (DWEMMC_CMD, MmcCmd);
• ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |

•        DWEMMC_INT_RCRC | DWEMMC_INT_RE;
  

• ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
• do {
• MicroSecondDelay(500);
• Data = MmioRead32 (DWEMMC_RINTSTS);
• if (Data & ErrMask) {

•  return EFI_DEVICE_ERROR;
  

• }
• if (Data & DWEMMC_INT_DTO) { // Transfer Done

•  break;
  

• }
• } while (!(Data & DWEMMC_INT_CMD_DONE));
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcSendCommand (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_CMD MmcCmd,
• IN UINT32 Argument
• )

+{

• UINT32 Cmd = 0;
• EFI_STATUS Status = EFI_SUCCESS;
• switch (MMC_GET_INDX(MmcCmd)) {
• case MMC_INDX(0):
• Cmd = BIT_CMD_SEND_INIT;
• break;
• case MMC_INDX(1):
• Cmd = BIT_CMD_RESPONSE_EXPECT;
• break;
• case MMC_INDX(2):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |

•       BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
  

• break;
• case MMC_INDX(3):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_SEND_INIT;
  

• break;
• case MMC_INDX(7):
• if (Argument)

•    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  

• else

•    Cmd = 0;
  

• break;
• case MMC_INDX(8):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(9):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_LONG_RESPONSE;
  

• break;
• case MMC_INDX(12):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_STOP_ABORT_CMD;
  

• break;
• case MMC_INDX(13):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(16):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(17):
• case MMC_INDX(18):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(24):
• case MMC_INDX(25):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(30):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED;
  

• break;
• default:
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
• break;
• }
• Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
• if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
• mDwEmmcCommand = Cmd;
• mDwEmmcArgument = Argument;
• } else {
• Status = SendCommand (Cmd, Argument);
• }
• return Status;

+}

+EFI_STATUS +DwEmmcReceiveResponse (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_RESPONSE_TYPE Type,
• IN UINT32* Buffer
• )

+{

• if (Buffer == NULL) {
• return EFI_INVALID_PARAMETER;
• }
• if ( (Type == MMC_RESPONSE_TYPE_R1)

•  || (Type == MMC_RESPONSE_TYPE_R1b)
  

•  || (Type == MMC_RESPONSE_TYPE_R3)
  

•  || (Type == MMC_RESPONSE_TYPE_R6)
  

•  || (Type == MMC_RESPONSE_TYPE_R7))
  

• {
• Buffer[0] = MmioRead32 (DWEMMC_RESP0);
• } else if (Type == MMC_RESPONSE_TYPE_R2) {
• Buffer[0] = MmioRead32 (DWEMMC_RESP0);
• Buffer[1] = MmioRead32 (DWEMMC_RESP1);
• Buffer[2] = MmioRead32 (DWEMMC_RESP2);
• Buffer[3] = MmioRead32 (DWEMMC_RESP3);
• }
• return EFI_SUCCESS;

+}

+EFI_STATUS +PrepareDmaData (

• IN DWEMMC_IDMAC_DESCRIPTOR* IdmacDesc,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• UINTN Cnt, Blks, Idx, LastIdx;
• Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
• Length = DWEMMC_BLOCK_SIZE * Blks;
• for (Idx = 0; Idx < Cnt; Idx++) {
• (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |

•                          DWEMMC_IDMAC_DES0_DIC;
  

• (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
• /* Buffer Address */
• (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
• /* Next Descriptor Address */
• (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +

•                                   (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
  

• }
• /* First Descriptor */
• IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
• /* Last Descriptor */
• LastIdx = Cnt - 1;
• (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
• (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
• (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -

•                                                  (LastIdx * DWEMMC_DMA_BUF_SIZE));
  

• /* Set the Next field of Last Descriptor */
• (IdmacDesc + LastIdx)->Des3 = 0;
• MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
• return EFI_SUCCESS;

+}

+VOID +StartDma (

• UINTN Length
• )

+{

• UINT32 Data;
• Data = MmioRead32 (DWEMMC_CTRL);
• Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
• MmioWrite32 (DWEMMC_CTRL, Data);
• Data = MmioRead32 (DWEMMC_BMOD);
• Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
• MmioWrite32 (DWEMMC_BMOD, Data);
• MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
• MmioWrite32 (DWEMMC_BYTCNT, Length);

+}

+EFI_STATUS +DwEmmcReadBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• EFI_STATUS Status;
• UINT32 DescPages, CountPerPage, Count;
• EFI_TPL Tpl;
• Tpl = gBS->RaiseTPL (TPL_NOTIFY);
• CountPerPage = EFI_PAGE_SIZE / 16;
• Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• DescPages = (Count + CountPerPage - 1) / CountPerPage;
• InvalidateDataCacheRange (Buffer, Length);
• Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
• if (EFI_ERROR (Status)) {
• goto out;
• }
• WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
• StartDma (Length);
• Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
• if (EFI_ERROR (Status)) {
• DEBUG ((EFI_D_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
• goto out;
• }

+out:

• // Restore Tpl
• gBS->RestoreTPL (Tpl);
• return Status;

+}

+EFI_STATUS +DwEmmcWriteBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• EFI_STATUS Status;
• UINT32 DescPages, CountPerPage, Count;
• EFI_TPL Tpl;
• Tpl = gBS->RaiseTPL (TPL_NOTIFY);
• CountPerPage = EFI_PAGE_SIZE / 16;
• Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• DescPages = (Count + CountPerPage - 1) / CountPerPage;
• WriteBackDataCacheRange (Buffer, Length);
• Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
• if (EFI_ERROR (Status)) {
• goto out;
• }
• WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
• StartDma (Length);
• Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
• if (EFI_ERROR (Status)) {
• DEBUG ((EFI_D_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
• goto out;
• }

+out:

• // Restore Tpl
• gBS->RestoreTPL (Tpl);
• return Status;

+}

+EFI_STATUS +DwEmmcSetIos (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN UINT32 BusClockFreq,
• IN UINT32 BusWidth,
• IN UINT32 TimingMode
• )

+{

• EFI_STATUS Status = EFI_SUCCESS;
• UINT32 Data;
• if (TimingMode != EMMCBACKWARD) {
• Data = MmioRead32 (DWEMMC_UHSREG);
• switch (TimingMode) {
• case EMMCHS52DDR1V2:
• case EMMCHS52DDR1V8:

•  Data |= 1 << 16;
  

•  break;
  

• case EMMCHS52:
• case EMMCHS26:

•  Data &= ~(1 << 16);
  

•  break;
  

• default:

•  return EFI_UNSUPPORTED;
  

• }
• MmioWrite32 (DWEMMC_UHSREG, Data);
• }
• switch (BusWidth) {
• case 1:
• MmioWrite32 (DWEMMC_CTYPE, 0);
• break;
• case 4:
• MmioWrite32 (DWEMMC_CTYPE, 1);
• break;
• case 8:
• MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
• break;
• default:
• return EFI_UNSUPPORTED;
• }
• if (BusClockFreq) {
• Status = DwEmmcSetClock (BusClockFreq);
• }
• return Status;

+}

+BOOLEAN +DwEmmcIsMultiBlock (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+EFI_MMC_HOST_PROTOCOL gMciHost = {

• MMC_HOST_PROTOCOL_REVISION,
• DwEmmcIsCardPresent,
• DwEmmcIsReadOnly,
• DwEmmcBuildDevicePath,
• DwEmmcNotifyState,
• DwEmmcSendCommand,
• DwEmmcReceiveResponse,
• DwEmmcReadBlockData,
• DwEmmcWriteBlockData,
• DwEmmcSetIos,
• DwEmmcIsMultiBlock

+};

+EFI_STATUS +DwEmmcDxeInitialize (

• IN EFI_HANDLE ImageHandle,
• IN EFI_SYSTEM_TABLE *SystemTable
• )

+{

• EFI_STATUS Status;
• EFI_HANDLE Handle;
• Handle = NULL;
• gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
• if (gpIdmacDesc == NULL) {
• return EFI_BUFFER_TOO_SMALL;
• }
• DEBUG ((EFI_D_BLKIO, "DwEmmcDxeInitialize()\n"));
• //Publish Component Name, BlockIO protocol interfaces
• Status = gBS->InstallMultipleProtocolInterfaces (

•              &Handle,
  

•              &gEfiMmcHostProtocolGuid,         &gMciHost,
  

•              NULL
  

•              );
  

• ASSERT_EFI_ERROR (Status);
• return EFI_SUCCESS;

+} diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec new file mode 100644 index 0000000..b281b93 --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec @@ -0,0 +1,42 @@ +#/** @file +# Framework Module Development Environment Industry Standards +# +# This Package provides headers and libraries that conform to EFI/PI Industry standards. +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR> +# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/

+[Defines]

• DEC_SPECIFICATION = 0x00010005
• PACKAGE_NAME = OpenPlatformDriversMmcDwEmmcDxePkg
• PACKAGE_GUID = 3869905e-c96c-4d20-9bfb-3b9d71bb900c
• PACKAGE_VERSION = 0.1

+################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################

+[Guids.common]

• gDwEmmcDxeTokenSpaceGuid = { 0x6fdd76a9, 0xf220, 0x4f1d, { 0x9c, 0xcf, 0xbc, 0x2d, 0x68, 0x29, 0xab, 0x9c }}

+[PcdsFixedAtBuild.common]

• # DwEmmc Driver PCDs
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000001
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000002

diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf new file mode 100644 index 0000000..f23494c --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf @@ -0,0 +1,55 @@ +#/** @file +# INF file for the eMMC Host Protocol implementation for the DesignWare MMC. +# +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = DwEmmcDxe
• FILE_GUID = b549f005-4bd4-4020-a0cb-06f42bda68c3
• MODULE_TYPE = DXE_DRIVER
• VERSION_STRING = 1.0
• ENTRY_POINT = DwEmmcDxeInitialize

+[Sources.common]

• DwEmmcDxe.c

+[Packages]

• EmbeddedPkg/EmbeddedPkg.dec
• MdePkg/MdePkg.dec
• OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec

+[LibraryClasses]

• ArmLib
• BaseLib
• BaseMemoryLib
• CacheMaintenanceLib
• IoLib
• MemoryAllocationLib
• TimerLib
• UefiDriverEntryPoint
• UefiLib

+[Protocols]

• gEfiCpuArchProtocolGuid
• gEfiDevicePathProtocolGuid
• gEfiMmcHostProtocolGuid

+[Pcd]

• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz

+[Depex]

• TRUE

-- 2.7.4

On 29 November 2016 at 20:01, Leif Lindholm leif.lindholm@linaro.org wrote:

On Wed, Nov 23, 2016 at 03:12:28PM +0800, Haojian Zhuang wrote:

...

Support designware emmc controller.

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang haojian.zhuang@linaro.org

---

Drivers/Mmc/DwEmmcDxe/DwEmmc.h | 128 +++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c | 651 ++++++++++++++++++++++++++++++++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec | 42 +++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf | 55 +++ 4 files changed, 876 insertions(+) create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmc.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf

diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmc.h b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h new file mode 100644 index 0000000..999b584 --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmc.h @@ -0,0 +1,128 @@ +/** @file +* +* Copyright (c) 2014, Linaro Limited. All rights reserved. +* Copyright (c) 2014, Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __DWEMMC_H__ +#define __DWEMMC_H__

+#include <Protocol/EmbeddedGpio.h>

+// DW MMC Registers +#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)

So, we already have tons of drivers that use a Pcd for a base address so that only one of them can exist in a system. This is not cause for rejecting a driver.

The existing HiKey port has two versions of this driver, one for the eMMC and one for the SD, where both have deviated from the common ancestor to address various issues that existed either in the code or in the hardware.

So I agree we should not reject this contribution, but at the same time we should not accept the forked SD version.

But I would be very, very happy if you had time to look into Ard's recent non-discoverable patchset, and perhaps the way the guys at SemiHalf have used it for their Armada 70x0 port.

This driver would be a lot nicer if written to that interface.

...

+#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004) +#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008) +#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c) +#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)

Tabs again. Please untabify.

...

+#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014) +#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018) +#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c) +#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020) +#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024) +#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028) +#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c) +#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030) +#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034) +#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038) +#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c) +#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044) +#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048) +#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c) +#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064) +#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074) +#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080) +#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088) +#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c) +#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090) +#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094) +#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098) +#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)

+#define CMD_UPDATE_CLK 0x80202000 +#define CMD_START_BIT (1 << 31)

+#define MMC_8BIT_MODE (1 << 16)

+#define BIT_CMD_RESPONSE_EXPECT (1 << 6) +#define BIT_CMD_LONG_RESPONSE (1 << 7) +#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) +#define BIT_CMD_DATA_EXPECTED (1 << 9) +#define BIT_CMD_READ (0 << 10) +#define BIT_CMD_WRITE (1 << 10) +#define BIT_CMD_BLOCK_TRANSFER (0 << 11) +#define BIT_CMD_STREAM_TRANSFER (1 << 11) +#define BIT_CMD_SEND_AUTO_STOP (1 << 12) +#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) +#define BIT_CMD_STOP_ABORT_CMD (1 << 14) +#define BIT_CMD_SEND_INIT (1 << 15) +#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) +#define BIT_CMD_READ_CEATA_DEVICE (1 << 22) +#define BIT_CMD_CCS_EXPECTED (1 << 23) +#define BIT_CMD_ENABLE_BOOT (1 << 24) +#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) +#define BIT_CMD_DISABLE_BOOT (1 << 26) +#define BIT_CMD_MANDATORY_BOOT (0 << 27) +#define BIT_CMD_ALTERNATE_BOOT (1 << 27) +#define BIT_CMD_VOLT_SWITCH (1 << 28) +#define BIT_CMD_USE_HOLD_REG (1 << 29) +#define BIT_CMD_START (1 << 31)

+#define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */ +#define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */ +#define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */ +#define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ +#define DWEMMC_INT_DRT (1 << 9) /* Data timeout */ +#define DWEMMC_INT_RTO (1 << 8) /* Response timeout */ +#define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */ +#define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */ +#define DWEMMC_INT_RXDR (1 << 5) +#define DWEMMC_INT_TXDR (1 << 4) +#define DWEMMC_INT_DTO (1 << 3) /* Data trans over */ +#define DWEMMC_INT_CMD_DONE (1 << 2) +#define DWEMMC_INT_RE (1 << 1)

+#define DWEMMC_IDMAC_DES0_DIC (1 << 1) +#define DWEMMC_IDMAC_DES0_LD (1 << 2) +#define DWEMMC_IDMAC_DES0_FS (1 << 3) +#define DWEMMC_IDMAC_DES0_CH (1 << 4) +#define DWEMMC_IDMAC_DES0_ER (1 << 5) +#define DWEMMC_IDMAC_DES0_CES (1 << 30) +#define DWEMMC_IDMAC_DES0_OWN (1 << 31) +#define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff) +#define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) +#define DWEMMC_IDMAC_SWRESET (1 << 0) +#define DWEMMC_IDMAC_FB (1 << 1) +#define DWEMMC_IDMAC_ENABLE (1 << 7)

+#define EMMC_FIX_RCA 6

+/* bits in MMC0_CTRL */ +#define DWEMMC_CTRL_RESET (1 << 0) +#define DWEMMC_CTRL_FIFO_RESET (1 << 1) +#define DWEMMC_CTRL_DMA_RESET (1 << 2) +#define DWEMMC_CTRL_INT_EN (1 << 4) +#define DWEMMC_CTRL_DMA_EN (1 << 5) +#define DWEMMC_CTRL_IDMAC_EN (1 << 25) +#define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)

+#define DWEMMC_STS_DATA_BUSY (1 << 9)

+#define DWEMMC_FIFO_TWMARK(x) (x & 0xfff) +#define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16) +#define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)

+#define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16) +#define DWEMMC_CARD_RD_THR_EN (1 << 0)

+#endif // __DWEMMC_H__ diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c new file mode 100644 index 0000000..cf75e1c --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c @@ -0,0 +1,651 @@ +/** @file

• This file implement the MMC Host Protocol for the DesignWare eMMC.
• Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
• Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved.
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#include <Library/BaseMemoryLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/TimerLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Protocol/MmcHost.h>

+#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h>

Could you insert these two, alphabetically sorted, in the already sorted block above?

...

+#include "DwEmmc.h"

+#define DWEMMC_DESC_PAGE 1 +#define DWEMMC_BLOCK_SIZE 512 +#define DWEMMC_DMA_BUF_SIZE (512 * 8) +#define DWEMMC_MAX_DESC_PAGES 512

+typedef struct {

• UINT32 Des0;
• UINT32 Des1;
• UINT32 Des2;
• UINT32 Des3;

+} DWEMMC_IDMAC_DESCRIPTOR;

+EFI_MMC_HOST_PROTOCOL *gpMmcHost; +DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc; +EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID; +STATIC UINT32 mDwEmmcCommand; +STATIC UINT32 mDwEmmcArgument;

+EFI_STATUS +DwEmmcReadBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• );

+BOOLEAN +DwEmmcIsPowerOn (

• VOID
• )

+{

• return TRUE;

+}

+EFI_STATUS +DwEmmcInitialize (

• VOID
• )

+{

• DEBUG ((EFI_D_BLKIO, "DwEmmcInitialize()"));

BaseTools/Scripts/PatchCheck.py will warn you that EFI_D_BLKIO is no longer the preferred macro to use, and that DEBUG_BLKIO is better. It would be good if you could run the set through PatchCheck for v2.

...

• return EFI_SUCCESS;

+}

+BOOLEAN +DwEmmcIsCardPresent (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+BOOLEAN +DwEmmcIsReadOnly (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return FALSE;

+}

+BOOLEAN +DwEmmcIsDmaSupported (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+EFI_STATUS +DwEmmcBuildDevicePath (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
• )

+{

• EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
• NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
• CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
• *DevicePath = NewDevicePathNode;
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcUpdateClock (

• VOID
• )

+{

• UINT32 Data;
• /* CMD_UPDATE_CLK */
• Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |

•  BIT_CMD_START;
  

• MmioWrite32 (DWEMMC_CMD, Data);
• while (1) {
• Data = MmioRead32 (DWEMMC_CMD);
• if (!(Data & CMD_START_BIT)) {

•  break;
  

• }
• Data = MmioRead32 (DWEMMC_RINTSTS);
• if (Data & DWEMMC_INT_HLE) {

•  Print (L"failed to update mmc clock frequency\n");
  

•  return EFI_DEVICE_ERROR;
  

• }
• }
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcSetClock (

• IN UINTN ClockFreq
• )

+{

• UINT32 Divider, Rate, Data;
• EFI_STATUS Status;
• BOOLEAN Found = FALSE;
• for (Divider = 1; Divider < 256; Divider++) {
• Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
• if ((Rate / (2 * Divider)) <= ClockFreq) {

•  Found = TRUE;
  

•  break;
  

• }
• }
• if (Found == FALSE) {
• return EFI_NOT_FOUND;
• }
• // Wait until MMC is idle
• do {
• Data = MmioRead32 (DWEMMC_STATUS);
• } while (Data & DWEMMC_STS_DATA_BUSY);
• // Disable MMC clock first
• MmioWrite32 (DWEMMC_CLKENA, 0);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• MmioWrite32 (DWEMMC_CLKDIV, Divider);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• // Enable MMC clock
• MmioWrite32 (DWEMMC_CLKENA, 1);
• MmioWrite32 (DWEMMC_CLKSRC, 0);
• Status = DwEmmcUpdateClock ();
• ASSERT (!EFI_ERROR (Status));
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcNotifyState (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_STATE State
• )

+{

• UINT32 Data;
• EFI_STATUS Status;
• switch (State) {
• case MmcInvalidState:
• ASSERT (0);

Should this not return something other than EFI_SUCCESS for RELEASE builds?

...

• break;
• case MmcHwInitializationState:
• MmioWrite32 (DWEMMC_PWREN, 1);
• // If device already turn on then restart it
• Data = DWEMMC_CTRL_RESET_ALL;
• MmioWrite32 (DWEMMC_CTRL, Data);
• do {

•  // Wait until reset operation finished
  

•  Data = MmioRead32 (DWEMMC_CTRL);
  

• } while (Data & DWEMMC_CTRL_RESET_ALL);
• // Setup clock that could not be higher than 400KHz.
• Status = DwEmmcSetClock (400000);
• ASSERT (!EFI_ERROR (Status));
• MicroSecondDelay (100);

Why the delay? Does this also need a barrier?

...

• MmioWrite32 (DWEMMC_RINTSTS, ~0);
• MmioWrite32 (DWEMMC_INTMASK, 0);
• MmioWrite32 (DWEMMC_TMOUT, ~0);
• MmioWrite32 (DWEMMC_IDINTEN, 0);
• MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
• MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
• do {

•  Data = MmioRead32 (DWEMMC_BMOD);
  

• } while (Data & DWEMMC_IDMAC_SWRESET);
• break;
• case MmcIdleState:
• break;
• case MmcReadyState:
• break;
• case MmcIdentificationState:
• break;
• case MmcStandByState:
• break;
• case MmcTransferState:
• break;
• case MmcSendingDataState:
• break;
• case MmcReceiveDataState:
• break;
• case MmcProgrammingState:
• break;
• case MmcDisconnectState:
• break;
• default:
• ASSERT (0);
• }
• return EFI_SUCCESS;

+}

+// Need to prepare DMA buffer first before sending commands to MMC card +BOOLEAN +IsPendingReadCommand (

• IN MMC_CMD MmcCmd
• )

+{

• UINTN Mask;
• Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
• if ((MmcCmd & Mask) == Mask) {
• return TRUE;
• }
• return FALSE;

+}

+BOOLEAN +IsPendingWriteCommand (

• IN MMC_CMD MmcCmd
• )

+{

• UINTN Mask;
• Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
• if ((MmcCmd & Mask) == Mask) {
• return TRUE;
• }
• return FALSE;

+}

+EFI_STATUS +SendCommand (

• IN MMC_CMD MmcCmd,
• IN UINT32 Argument
• )

+{

• UINT32 Data, ErrMask;
• // Wait until MMC is idle
• do {
• Data = MmioRead32 (DWEMMC_STATUS);
• } while (Data & DWEMMC_STS_DATA_BUSY);
• MmioWrite32 (DWEMMC_RINTSTS, ~0);
• MmioWrite32 (DWEMMC_CMDARG, Argument);
• MmioWrite32 (DWEMMC_CMD, MmcCmd);
• ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |

•        DWEMMC_INT_RCRC | DWEMMC_INT_RE;
  

• ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
• do {
• MicroSecondDelay(500);
• Data = MmioRead32 (DWEMMC_RINTSTS);
• if (Data & ErrMask) {

•  return EFI_DEVICE_ERROR;
  

• }
• if (Data & DWEMMC_INT_DTO) { // Transfer Done

•  break;
  

• }
• } while (!(Data & DWEMMC_INT_CMD_DONE));
• return EFI_SUCCESS;

+}

+EFI_STATUS +DwEmmcSendCommand (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_CMD MmcCmd,
• IN UINT32 Argument
• )

+{

• UINT32 Cmd = 0;
• EFI_STATUS Status = EFI_SUCCESS;
• switch (MMC_GET_INDX(MmcCmd)) {
• case MMC_INDX(0):
• Cmd = BIT_CMD_SEND_INIT;
• break;
• case MMC_INDX(1):
• Cmd = BIT_CMD_RESPONSE_EXPECT;
• break;
• case MMC_INDX(2):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |

•       BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
  

• break;
• case MMC_INDX(3):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_SEND_INIT;
  

• break;
• case MMC_INDX(7):
• if (Argument)

•    Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  

• else

•    Cmd = 0;
  

• break;
• case MMC_INDX(8):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(9):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_LONG_RESPONSE;
  

• break;
• case MMC_INDX(12):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_STOP_ABORT_CMD;
  

• break;
• case MMC_INDX(13):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(16):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(17):
• case MMC_INDX(18):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(24):
• case MMC_INDX(25):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
  

•       BIT_CMD_WAIT_PRVDATA_COMPLETE;
  

• break;
• case MMC_INDX(30):
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |

•       BIT_CMD_DATA_EXPECTED;
  

• break;
• default:
• Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
• break;
• }
• Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
• if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
• mDwEmmcCommand = Cmd;
• mDwEmmcArgument = Argument;
• } else {
• Status = SendCommand (Cmd, Argument);
• }
• return Status;

+}

+EFI_STATUS +DwEmmcReceiveResponse (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN MMC_RESPONSE_TYPE Type,
• IN UINT32* Buffer
• )

+{

• if (Buffer == NULL) {
• return EFI_INVALID_PARAMETER;
• }
• if ( (Type == MMC_RESPONSE_TYPE_R1)

•  || (Type == MMC_RESPONSE_TYPE_R1b)
  

•  || (Type == MMC_RESPONSE_TYPE_R3)
  

•  || (Type == MMC_RESPONSE_TYPE_R6)
  

•  || (Type == MMC_RESPONSE_TYPE_R7))
  

• {
• Buffer[0] = MmioRead32 (DWEMMC_RESP0);
• } else if (Type == MMC_RESPONSE_TYPE_R2) {
• Buffer[0] = MmioRead32 (DWEMMC_RESP0);
• Buffer[1] = MmioRead32 (DWEMMC_RESP1);
• Buffer[2] = MmioRead32 (DWEMMC_RESP2);
• Buffer[3] = MmioRead32 (DWEMMC_RESP3);
• }
• return EFI_SUCCESS;

+}

+EFI_STATUS +PrepareDmaData (

• IN DWEMMC_IDMAC_DESCRIPTOR* IdmacDesc,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• UINTN Cnt, Blks, Idx, LastIdx;
• Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
• Length = DWEMMC_BLOCK_SIZE * Blks;
• for (Idx = 0; Idx < Cnt; Idx++) {
• (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |

•                          DWEMMC_IDMAC_DES0_DIC;
  

• (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
• /* Buffer Address */
• (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
• /* Next Descriptor Address */
• (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +

•                                   (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
  

• }
• /* First Descriptor */
• IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
• /* Last Descriptor */
• LastIdx = Cnt - 1;
• (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
• (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
• (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -

•                                                  (LastIdx * DWEMMC_DMA_BUF_SIZE));
  

• /* Set the Next field of Last Descriptor */
• (IdmacDesc + LastIdx)->Des3 = 0;
• MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
• return EFI_SUCCESS;

+}

+VOID +StartDma (

• UINTN Length
• )

+{

• UINT32 Data;
• Data = MmioRead32 (DWEMMC_CTRL);
• Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
• MmioWrite32 (DWEMMC_CTRL, Data);
• Data = MmioRead32 (DWEMMC_BMOD);
• Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
• MmioWrite32 (DWEMMC_BMOD, Data);
• MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
• MmioWrite32 (DWEMMC_BYTCNT, Length);

+}

+EFI_STATUS +DwEmmcReadBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• EFI_STATUS Status;
• UINT32 DescPages, CountPerPage, Count;
• EFI_TPL Tpl;
• Tpl = gBS->RaiseTPL (TPL_NOTIFY);
• CountPerPage = EFI_PAGE_SIZE / 16;
• Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• DescPages = (Count + CountPerPage - 1) / CountPerPage;
• InvalidateDataCacheRange (Buffer, Length);
• Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
• if (EFI_ERROR (Status)) {
• goto out;
• }
• WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
• StartDma (Length);
• Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
• if (EFI_ERROR (Status)) {
• DEBUG ((EFI_D_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
• goto out;
• }

+out:

• // Restore Tpl
• gBS->RestoreTPL (Tpl);
• return Status;

+}

+EFI_STATUS +DwEmmcWriteBlockData (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN EFI_LBA Lba,
• IN UINTN Length,
• IN UINT32* Buffer
• )

+{

• EFI_STATUS Status;
• UINT32 DescPages, CountPerPage, Count;
• EFI_TPL Tpl;
• Tpl = gBS->RaiseTPL (TPL_NOTIFY);
• CountPerPage = EFI_PAGE_SIZE / 16;
• Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
• DescPages = (Count + CountPerPage - 1) / CountPerPage;
• WriteBackDataCacheRange (Buffer, Length);
• Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
• if (EFI_ERROR (Status)) {
• goto out;
• }
• WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
• StartDma (Length);
• Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
• if (EFI_ERROR (Status)) {
• DEBUG ((EFI_D_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
• goto out;
• }

+out:

• // Restore Tpl
• gBS->RestoreTPL (Tpl);
• return Status;

+}

+EFI_STATUS +DwEmmcSetIos (

• IN EFI_MMC_HOST_PROTOCOL *This,
• IN UINT32 BusClockFreq,
• IN UINT32 BusWidth,
• IN UINT32 TimingMode
• )

+{

• EFI_STATUS Status = EFI_SUCCESS;
• UINT32 Data;
• if (TimingMode != EMMCBACKWARD) {
• Data = MmioRead32 (DWEMMC_UHSREG);
• switch (TimingMode) {
• case EMMCHS52DDR1V2:
• case EMMCHS52DDR1V8:

•  Data |= 1 << 16;
  

•  break;
  

• case EMMCHS52:
• case EMMCHS26:

•  Data &= ~(1 << 16);
  

•  break;
  

• default:

•  return EFI_UNSUPPORTED;
  

• }
• MmioWrite32 (DWEMMC_UHSREG, Data);
• }
• switch (BusWidth) {
• case 1:
• MmioWrite32 (DWEMMC_CTYPE, 0);
• break;
• case 4:
• MmioWrite32 (DWEMMC_CTYPE, 1);
• break;
• case 8:
• MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
• break;
• default:
• return EFI_UNSUPPORTED;
• }
• if (BusClockFreq) {
• Status = DwEmmcSetClock (BusClockFreq);
• }
• return Status;

+}

+BOOLEAN +DwEmmcIsMultiBlock (

• IN EFI_MMC_HOST_PROTOCOL *This
• )

+{

• return TRUE;

+}

+EFI_MMC_HOST_PROTOCOL gMciHost = {

• MMC_HOST_PROTOCOL_REVISION,
• DwEmmcIsCardPresent,
• DwEmmcIsReadOnly,
• DwEmmcBuildDevicePath,
• DwEmmcNotifyState,
• DwEmmcSendCommand,
• DwEmmcReceiveResponse,
• DwEmmcReadBlockData,
• DwEmmcWriteBlockData,
• DwEmmcSetIos,
• DwEmmcIsMultiBlock

+};

+EFI_STATUS +DwEmmcDxeInitialize (

• IN EFI_HANDLE ImageHandle,
• IN EFI_SYSTEM_TABLE *SystemTable
• )

+{

• EFI_STATUS Status;
• EFI_HANDLE Handle;
• Handle = NULL;
• gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
• if (gpIdmacDesc == NULL) {
• return EFI_BUFFER_TOO_SMALL;
• }
• DEBUG ((EFI_D_BLKIO, "DwEmmcDxeInitialize()\n"));
• //Publish Component Name, BlockIO protocol interfaces
• Status = gBS->InstallMultipleProtocolInterfaces (

•              &Handle,
  

•              &gEfiMmcHostProtocolGuid,         &gMciHost,
  

•              NULL
  

•              );
  

• ASSERT_EFI_ERROR (Status);
• return EFI_SUCCESS;

+} diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec new file mode 100644 index 0000000..b281b93 --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec @@ -0,0 +1,42 @@ +#/** @file +# Framework Module Development Environment Industry Standards +# +# This Package provides headers and libraries that conform to EFI/PI Industry standards. +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2012-2014, ARM Ltd. All rights reserved.<BR> +# Copyright (c) 2015-2016, Linaro. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/

+[Defines]

• DEC_SPECIFICATION = 0x00010005
• PACKAGE_NAME = OpenPlatformDriversMmcDwEmmcDxePkg

Can probably drop "OpenPlatformDrivers".

...

• PACKAGE_GUID = 3869905e-c96c-4d20-9bfb-3b9d71bb900c
• PACKAGE_VERSION = 0.1

+################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################

+[Guids.common]

• gDwEmmcDxeTokenSpaceGuid = { 0x6fdd76a9, 0xf220, 0x4f1d, { 0x9c, 0xcf, 0xbc, 0x2d, 0x68, 0x29, 0xab, 0x9c }}

Again, this looks a bit funky to me. Is this working around some missing [Protocols] dependency?

Regards,

Leif

...

+[PcdsFixedAtBuild.common]

• # DwEmmc Driver PCDs
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x0|UINT32|0x00000001
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000002

diff --git a/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf new file mode 100644 index 0000000..f23494c --- /dev/null +++ b/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf @@ -0,0 +1,55 @@ +#/** @file +# INF file for the eMMC Host Protocol implementation for the DesignWare MMC. +# +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# Copyright (c) 2014-2016, Hisilicon Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = DwEmmcDxe
• FILE_GUID = b549f005-4bd4-4020-a0cb-06f42bda68c3
• MODULE_TYPE = DXE_DRIVER
• VERSION_STRING = 1.0
• ENTRY_POINT = DwEmmcDxeInitialize

+[Sources.common]

• DwEmmcDxe.c

+[Packages]

• EmbeddedPkg/EmbeddedPkg.dec
• MdePkg/MdePkg.dec
• OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec

+[LibraryClasses]

• ArmLib
• BaseLib
• BaseMemoryLib
• CacheMaintenanceLib
• IoLib
• MemoryAllocationLib
• TimerLib
• UefiDriverEntryPoint
• UefiLib

+[Protocols]

• gEfiCpuArchProtocolGuid
• gEfiDevicePathProtocolGuid
• gEfiMmcHostProtocolGuid

+[Pcd]

• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
• gDwEmmcDxeTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz

+[Depex]

• TRUE

-- 2.7.4