Linaro-uefi

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[linaro-uefi v1] D05/ACPI: fix an error of sas0/sas1 interrupts map

by Chenhui Sun

From: Heyi Guo <heyi.guo(a)linaro.org> the interrupt 74 was omited and 160 was added by mistake. correct this error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiaofei Tan <tanxiaofei(a)huawei.com> Revied-by: John Garry <john.garry(a)huawei.com> --- .../Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 72 +++++++++++----------- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 72 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl index 528f8a3..9ee9d83 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl @@ -103,24 +103,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, } Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) @@ -156,24 +156,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, } Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 0c24bce..93beb95 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -25,24 +25,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, } Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2") @@ -100,24 +100,24 @@ Scope(_SB) { 64,65,66,67,68, 69,70,71,72,73, - 75,76,77,78,79, - 80,81,82,83,84, - 85,86,87,88,89, - 90,91,92,93,94, - 95,96,97,98,99, - 100,101,102,103,104, - 105,106,107,108,109, - 110,111,112,113,114, - 115,116,117,118,119, - 120,121,122,123,124, - 125,126,127,128,129, - 130,131,132,133,134, - 135,136,137,138,139, - 140,141,142,143,144, - 145,146,147,148,149, - 150,151,152,153,154, - 155,156,157,158,159, - 160, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, } Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3") -- 1.9.1

7 years, 11 months

[PATCH] Hisilicon D03/D05: add SCSI cdb16 command

by Heyi Guo

From: heyi.guo <guoheyi(a)huawei.com> This patch resolves the issue 2393: https://bugs.linaro.org. The cdb16 command should be used if the hard disk size larger than 4TB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun <sunchenhui(a)huawei.com> Signed-off-by: Jason Zhang <zhangjinsong2(a)huawei.com> --- .../Binary/D03/Drivers/Sas/SasDriverDxe.efi | Bin 210752 -> 208288 bytes .../Binary/D05/Drivers/Sas/SasDriverDxe.efi | Bin 210400 -> 230912 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi index b956b19..19cd038 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi and b/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDriverDxe.efi differ diff --git a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi index 6021d12..8d9ecd2 100644 Binary files a/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi and b/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDriverDxe.efi differ -- 1.9.1

7 years, 11 months

[linaro-uefi v2 0/4] Platforms/ARM/VExpress: Support for MM Standalone mode on AArch64 FVP Base

by achin.gupta＠arm.com

From: Achin Gupta <achin.gupta(a)arm.com> This patchset adds support for creating a MM Standalone image suitable for running on a Base FVP in the AArch64 execution state. The core support for instantiating MM Standalone mode is being developed in the following edk2-staging branch: https://github.com/tianocore/edk2-staging/tree/AArch64StandaloneMm This branch and the patchset should be combined to build a MM Standalone image. The instructions for this will be updated in edk2-staging later. The changes in this series are aimed at: 1. partitioning DRAM to set aside memory for the MM Standalone image 2. including the necessary modules to instantiate the Standalone MM on the Base FVP This patchset should be staged in a separate branch until it is clearer how the MM Standalone image should be supported on common ARM platforms. The name of the branch should be the same as the edk2-staging branch i.e. AArch64StandaloneMm. Changelog since v1: - Introduced ARM_STANDALONE_MM_ENABLE define to encapsulate changes introduced in this series Achin Gupta (4): Platforms/ARM/VExpress: Size DRAM to accommodate Standalone MM image Platforms/ARM/VExpress: Define extents of MM communication buffer Platforms/ARM/VExpress: Include MM communication protocol driver Platforms/ARM/VExpress: Include UEFI Info application in FVP build Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 19 +++++++++++++++++++ Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.fdf | 6 ++++++ 2 files changed, 25 insertions(+) -- 1.9.1

7 years, 11 months

Hide SimpleFileSystem instance from UEFI shell

by Konrad Adamczyk

Hi everyone, I'd like to know if there's a way to hide SimpleFileSystem instance from boot entries? Currently we have some entries that are known to be sure not bootable (used only for configuration purposes) and we don't want to expose them to user. Thanks in advance. Best regards, Konrad Adamczyk

7 years, 12 months

A GIC problem on UEFI

by zhufuwengang

Hi ,all In the progress of UEFI porting, I had a big problem. The function GicV2DxeInitialize in ArmGicDxe.inf module produced a Synchronous Exception, when it executed MmioRead32 (mGicDistributorBase + ARM_GIC_ICDICTR). And I am also using GIC400. The GICD&GICC register base have been set correctly. Strangely enough, the MmioRead32 (mGicDistributorBase + ARM_GIC_ICDICTR) code can be executed successfully in Arm trusted firmware which is the previous stage of UEFI. And also, I tried to use a evaluation to analysis the exception and got the following error message. [cid:image001.png@01D25C42.2B95A4F0] I don't know whether the ArmGicDxe.inf module must be executed in a particular environment which have not been set correctly in the previous module of UEFI? By the way, I'm using dependency expression way to dispatch the DXE drivers on Poplar board. I don't know the main cause of this problem and how to solve it. Can you give me some advises? Best Regards, Wengang

8 years

[linaro-uefi] Hisilicon/D05: remove Eth2/Eth3/Eth6/Eth7 at dsdt table

by Heyi Guo

This patch is for https://bugs.linaro.org/show_bug.cgi?id=2714. As there are 4 physical NIC ports on D05 board, so we remove the other NIC ports that are used for extension. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun <sunchenhui(a)huawei.com> --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 543 --------------------- 1 file changed, 543 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 046257b..0c3af0a 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -550,28 +550,6 @@ Scope(_SB) }) } - Device (PRT2) - { - Name (_ADR, 0x2) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 2}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT3) - { - Name (_ADR, 0x3) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 3}, - Package () {"media-type", "fiber"}, - } - }) - } Device (PRT4) { @@ -651,30 +629,6 @@ Scope(_SB) }) } - Device (ETH2) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 2}, - } - }) - } - Device (ETH3) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF0}}, - Package () {"port-idx-in-ae", 3}, - } - }) - } Device (ROCE) { Name(_HID, "HISI00D1") @@ -732,502 +686,5 @@ Scope(_SB) }) } - /* for p1 */ - Device (DSF1) - { - - OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4) - Field(H3SR, DWordAcc, NoLock, Preserve) { - H3ST, 1, - , 31, //RESERVED - } - OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4) - Field(H4SR, DWordAcc, NoLock, Preserve) { - H4ST, 1, - , 31, //RESERVED - } - // DSAF RESET - OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8) - Field(DRER, DWordAcc, NoLock, Preserve) { - DRTE, 1, - , 31, //RESERVED - DRTD, 1, - , 31, //RESERVED - } - // NT RESET - OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8) - Field(NRER, DWordAcc, NoLock, Preserve) { - NRTE, 1, - , 31, //RESERVED - NRTD, 1, - , 31, //RESERVED - } - // XGE RESET - OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8) - Field(XRER, DWordAcc, NoLock, Preserve) { - XRTE, 31, - , 1, //RESERVED - XRTD, 31, - , 1, //RESERVED - } - - // GE RESET - OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16) - Field(GRTR, DWordAcc, NoLock, Preserve) { - GR0E, 30, - , 2, //RESERVED - GR0D, 30, - , 2, //RESERVED - GR1E, 18, - , 14, //RESERVED - GR1D, 18, - , 14, //RESERVED - } - // PPE RESET - OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8) - Field(PRTR, DWordAcc, NoLock, Preserve) { - PRTE, 10, - , 22, //RESERVED - PRTD, 10, - , 22, //RESERVED - } - - // RCB PPE COM RESET - OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8) - Field(RRTR, DWordAcc, NoLock, Preserve) { - RRTE, 1, - , 31, //RESERVED - RRTD, 1, - , 31, //RESERVED - } - - // RCB_2X COM RESET - OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8) - Field(RBTR, DWordAcc, NoLock, Preserve) { - RBTE, 1, - , 31, //RESERVED - RBTD, 1, - , 31, //RESERVED - } - - // Hilink access sel cfg reg - OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4) - Field(HSER, DWordAcc, NoLock, Preserve) { - HSEL, 2, // hilink_access_sel & hilink_access_wr_pul - , 30, // RESERVED - } - - // Serdes - OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000) - Field(H4LR, DWordAcc, NoLock, Preserve) { - H4L0, 16, // port0 - , 16, //RESERVED - Offset (0x400), - H4L1, 16, // port1 - , 16, //RESERVED - Offset (0x800), - H4L2, 16, // port2 - , 16, //RESERVED - Offset (0xc00), - H4L3, 16, // port3 - , 16, //RESERVED - } - OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800) - Field(H3LR, DWordAcc, NoLock, Preserve) { - H3L2, 16, // port4 - , 16, //RESERVED - Offset (0x400), - H3L3, 16, // port5 - , 16, //RESERVED - } - - Name (_HID, "HISI00B2") - Name (_CCA, 1) // Cache-coherent controller - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400c5000000, // Min Base Address - 0x400c588ffff, // Max Base Address - 0x0, // Translate - 0x890000 // Length - ) - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x400c7000000, // Min Base Address - 0x400c705ffff, // Max Base Address - 0x0, // Translate - 0x60000 // Length - ) - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, - 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, - 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, - 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, - 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, - 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, - 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, - 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, - 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, - 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, - 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, - 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, - } - Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8") - { - 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, - 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, - 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, - 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, - 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, - 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, - 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, - 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, - 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, - 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, - 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, - 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, - } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"mode", "6port-16rss"}, - Package () {"buf-size", 4096}, - Package () {"desc-num", 1024}, - } - }) - - //reset XGE port - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XRST, 2, Serialized) { - ShiftLeft (0x2082082, Arg0, Local0) - Or (Local0, 0x1, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset XGE core - //Arg0 : XGE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(XCRT, 2, Serialized) { - ShiftLeft (0x2080, Arg0, Local0) - - If (LEqual (Arg1, 0)) { - Store(Local0, XRTE) - } Else { - Store(Local0, XRTD) - } - } - - //reset GE port - //Arg0 : GE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(GRST, 2, Serialized) { - If (LLessEqual (Arg0, 5)) { - //Service port - ShiftLeft (0x2082082, Arg0, Local0) - ShiftLeft (0x1, Arg0, Local1) - - If (LEqual (Arg1, 0)) { - Store(Local1, GR1E) - Store(Local0, GR0E) - } Else { - Store(Local0, GR0D) - Store(Local1, GR1D) - } - } - } - - //reset PPE port - //Arg0 : PPE port index in dsaf - //Arg1 : 0 reset, 1 cancle reset - Method(PRST, 2, Serialized) { - ShiftLeft (0x1, Arg0, Local0) - If (LEqual (Arg1, 0)) { - Store(Local0, PRTE) - } Else { - Store(Local0, PRTD) - } - } - - // Set Serdes Loopback - //Arg0 : port - //Arg1 : 0 disable, 1 enable - Method(SRLP, 2, Serialized) { - ShiftLeft (Arg1, 10, Local0) - Switch (ToInteger(Arg0)) - { - case (0x0){ - Store (0, HSEL) - Store (H4L0, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L0) - } - case (0x1){ - Store (0, HSEL) - Store (H4L1, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L1) - } - case (0x2){ - Store (0, HSEL) - Store (H4L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L2) - } - case (0x3){ - Store (0, HSEL) - Store (H4L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H4L3) - } - case (0x4){ - Store (3, HSEL) - Store (H3L2, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L2) - } - case (0x5){ - Store (3, HSEL) - Store (H3L3, Local1) - And (Local1, 0xfffffbff, Local1) - Or (Local0, Local1, Local0) - Store (Local0, H3L3) - } - } - } - - //Reset - //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3) - //Arg1 : port - //Arg2 : 0 disable, 1 enable - Method(DRST, 3, Serialized) - { - Switch (ToInteger(Arg0)) - { - //DSAF reset - case (0x1) - { - Store (Arg2, Local0) - If (LEqual (Local0, 0)) - { - Store (0x1, DRTE) - Store (0x1, NRTE) - Sleep (10) - Store (0x1, RRTE) - Store (0x1, RBTE) - } - Else - { - Store (0x1, DRTD) - Store (0x1, NRTD) - Sleep (10) - Store (0x1, RRTD) - Store (0x1, RBTD) - } - } - //Reset PPE port - case (0x2) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - PRST (Local0, Local1) - } - - //Reset XGE core - case (0x3) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XCRT (Local0, Local1) - } - //Reset XGE port - case (0x4) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - XRST (Local0, Local1) - } - - //Reset GE port - case (0x5) - { - Store (Arg1, Local0) - Store (Arg2, Local1) - GRST (Local0, Local1) - } - } - } - - // _DSM Device Specific Method - // - // Arg0: UUID Unique function identifier - // Arg1: Integer Revision Level - // Arg2: Integer Function Index - // 0 : Return Supported Functions bit mask - // 1 : Reset Sequence - // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge) - // Arg3[1] : port index in dsaf - // Arg3[2] : 0 reset, 1 cancle reset - // 2 : Set Serdes Loopback - // Arg3[0] : port - // Arg3[1] : 0 disable, 1 enable - // 3 : LED op set - // Arg3[0] : op type - // Arg3[1] : port - // Arg3[2] : para - // 4 : Get port type (GE or XGE) - // Arg3[0] : port index in dsaf - // Return : 0 GE, 1 XGE - // 5 : Get sfp status - // Arg3[0] : port index in dsaf - // Return : 0 no sfp, 1 have sfp - // Arg3: Package Parameters - Method (_DSM, 4, Serialized) - { - If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A"))) - { - If (LEqual (Arg1, 0x00)) - { - Switch (ToInteger(Arg2)) - { - case (0x0) - { - Return (Buffer () {0x3F}) - } - - //Reset Sequence - case (0x1) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - Store (DeRefOf (Index (Arg3, 2)), Local2) - DRST (Local0, Local1, Local2) - } - - //Set Serdes Loopback - case (0x2) - { - Store (DeRefOf (Index (Arg3, 0)), Local0) - Store (DeRefOf (Index (Arg3, 1)), Local1) - SRLP (Local0, Local1) - } - - //LED op set - case (0x3) - { - - } - - // Get port type (GE or XGE) - case (0x4) - { - Store (0, Local1) - Store (DeRefOf (Index (Arg3, 0)), Local0) - If (LLessEqual (Local0, 3)) - { - // mac0: Hilink4 Lane0 - // mac1: Hilink4 Lane1 - // mac2: Hilink4 Lane2 - // mac3: Hilink4 Lane3 - Store (H4ST, Local1) - } - ElseIf (LLessEqual (Local0, 5)) - { - // mac4: Hilink3 Lane2 - // mac5: Hilink3 Lane3 - Store (H3ST, Local1) - } - - Return (Local1) - } - - //Get sfp status - case (0x5) - { - - } - } - } - } - Return (Buffer() {0x00}) - } - - Device (PRT6) - { - Name (_ADR, 0x6) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 0}, - Package () {"media-type", "fiber"}, - } - }) - } - Device (PRT7) - { - Name (_ADR, 0x7) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"reg", 1}, - Package () {"media-type", "fiber"}, - } - }) - } - } - - Device (ETH6) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF1}}, - Package () {"port-idx-in-ae", 0}, - } - }) - } - Device (ETH7) { - Name(_HID, "HISI00C2") - Name (_CCA, 1) // Cache-coherent controller - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes - Package () {"ae-handle", Package (){\_SB.DSF1}}, - Package () {"port-idx-in-ae", 1}, - } - }) - } } -- 1.9.1

8 years

[PATCH] FVP: ACPI Add iort and GICv3 ITS support

by Dennis Chen

Since ARM VExpress FVP platform will support some PCIe devices (e.g, SMMU Test Engine) behind the PCIe Root Complex and SMMUv3 which can generate PCI ITS-MSI/memory transaction to the core. Moreover, the IORT based SMMU patch has been merged into the linux kernel, in order to ease the testing/verification effort of those features, we need to integrate those ACPI tables (mcfg, iort...) into the FVP UEFI binary. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dennis Chen <dennis.chen(a)arm.com> Cc: Leif Lindholm <leif.lindholm(a)linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel(a)linaro.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com> Cc: Steve Capper <steve.capper(a)arm.com> --- Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf | 4 + Platforms/ARM/VExpress/AcpiTables/Madt.aslc | 54 ++++++------ Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl | 89 ++++++++++++++++++++ Platforms/ARM/VExpress/AcpiTables/mcfg.asl | 25 ++++++ Platforms/ARM/VExpress/AcpiTables/ssdt.asl | 98 ++++++++++++++++++++++ Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 + 6 files changed, 247 insertions(+), 24 deletions(-) create mode 100644 Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl create mode 100644 Platforms/ARM/VExpress/AcpiTables/mcfg.asl create mode 100644 Platforms/ARM/VExpress/AcpiTables/ssdt.asl diff --git a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf index 59d3238..000e83d 100644 --- a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf +++ b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf @@ -27,6 +27,9 @@ Fadt.aslc Gtdt.aslc Madt.aslc + mcfg.asl + ssdt.asl + iort-smmuv3.asl [Packages] ArmPkg/ArmPkg.dec @@ -41,3 +44,4 @@ gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGicItsBase diff --git a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc index bf90a9f..d2d9d9a 100644 --- a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc +++ b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc @@ -30,8 +30,15 @@ typedef struct { EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[8]; EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; EFI_ACPI_6_1_GICR_STRUCTURE Gicr; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicIts; } FVP_MULTIPLE_APIC_DESCRIPTION_TABLE; +#define FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr) \ + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( \ + GicId, AcpiCpuUid, Mpidr, \ + EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),\ + 0x2C02F000, 0x2C010000, 0x19, 0, 0) + #pragma pack () FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { @@ -47,33 +54,22 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // LocalApicAddress 0, // Flags }, + + /* Gic Interfaces array */ { - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), - EFI_ACPI_6_0_GICC_STRUCTURE_INIT( - 7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - 0x2C02F000, 0x2C010000, 0x19, 0, 0), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, 0, GET_MPID(0, 0)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, 1, GET_MPID(0, 1)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, 2, GET_MPID(0, 2)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, 3, GET_MPID(0, 3)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(4, 4, GET_MPID(1, 0)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(5, 5, GET_MPID(1, 1)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(6, 6, GET_MPID(1, 2)), + FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(7, 7, GET_MPID(1, 3)), }, + + /* GIC Distributor */ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3), + /* GIC Redistributor */ { EFI_ACPI_6_1_GICR, // UINT8 Type @@ -81,6 +77,16 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { EFI_ACPI_RESERVED_WORD, // UINT16 Reserved FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress 0x00200000, // UINT32 DiscoveryRangeLength + }, + + /* GIC ITS */ + { + EFI_ACPI_6_1_GIC_ITS, // UINT8 Type + sizeof(EFI_ACPI_6_1_GIC_ITS_STRUCTURE), // UINT8 Length + EFI_ACPI_RESERVED_WORD, // UINT16 Reserved + 0x00000000, // UINT32 GicItsId + FixedPcdGet64 (PcdGicItsBase), // UINT64 GicItsBaseAddress + EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved } }; diff --git a/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl b/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl new file mode 100644 index 0000000..6caee57 --- /dev/null +++ b/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl @@ -0,0 +1,89 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 0000029e +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "ARM " +[0008] Oem Table ID : "VExpress" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20150410 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000044 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS Group : 24-byte */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 + +/* SMMUv3 : 80-byte */ +[0001] Type : 04 +[0002] Length : 0050 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 0000003C + +[0008] Base Address : 000000002b400000 +[0004] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0004] Reserved : 00000000 +[0008] VATOS Address : 0000000000000000 +[0004] Model : 00000000 +[0004] Event GSIV : 6a/*4a*/ +[0004] PRI GSIV : 6b/*4b*/ +[0004] GERR GSIV : 6f/*4f*/ +[0004] Sync GSIV : 6d/*4d*/ +[0004] Input base : 00000000 +[0004] ID Count : 0000ffff +[0004] Output Base : 00000000 +[0004] Output Reference : 00000034 /* ITS Group node offset */ +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* RC 0 : 52-byte */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000000 + +[0004] Input base : 00000000 +[0004] ID Count : 0000ffff +[0004] Output Base : 00000000 +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + diff --git a/Platforms/ARM/VExpress/AcpiTables/mcfg.asl b/Platforms/ARM/VExpress/AcpiTables/mcfg.asl new file mode 100644 index 0000000..caa2b38 --- /dev/null +++ b/Platforms/ARM/VExpress/AcpiTables/mcfg.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20160212-64 + * Copyright (c) 2000 - 2016 Intel Corporation + * + * Template for [MCFG] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "MCFG" [Memory Mapped Configuration table] +[0004] Table Length : 0000003C +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 0000000040000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : 01 +[0004] Reserved : 00000000 diff --git a/Platforms/ARM/VExpress/AcpiTables/ssdt.asl b/Platforms/ARM/VExpress/AcpiTables/ssdt.asl new file mode 100644 index 0000000..08c7e7b --- /dev/null +++ b/Platforms/ARM/VExpress/AcpiTables/ssdt.asl @@ -0,0 +1,98 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20141107-64 [Feb 4 2015] + * Copyright (c) 2000 - 2015 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of ssdt.aml, Tue Aug 9 10:17:31 2016 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x00000168 (360) + * Revision 0x01 + * Checksum 0x42 + * OEM ID "ARMLTD" + * OEM Table ID "ARM-JUNO" + * OEM Revision 0x00000000 (0) + * Compiler ID "INTL" + * Compiler Version 0x20141107 (538185991) + */ +DefinitionBlock ("ssdt.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", 0x00000000) +{ + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Device (RP0) + { + Name (_ADR, 0xF0000000) // _ADR: Address + } + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0001, // Range Maximum + 0x0000, // Translation Offset + 0x0002, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x50000000, // Range Minimum + 0x5FFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x10000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */ + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, Zero, CDW1) + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + If (((SUPP & 0x16) != 0x16)) + { + CTRL &= 0x1E + } + + CTRL &= 0x1D + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + } + } +} + diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc index cf4b803..1d4db81 100644 --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc @@ -153,6 +153,7 @@ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000 + gArmTokenSpaceGuid.PcdGicItsBase|0x2f020000 # # ARM OS Loader -- 2.7.4

8 years

[PATCH] FVP: ACPI Add iort and GICv3 ITS support

by Dennis Chen

8 years

[PATCH] EFI: fix build for AARCH64

by Leif Lindholm

AARCH64 build was left out of initial version, so add to .dsc and set ACPI_MACHINE_WIDTH correctly. Also, acpidump.inf specified explicit per-architecture (but identical) CFLAGS. Rather than duplicating this further, use the same setting for all architectures until there is actually a need to diverge. Also update README to make it obvious AArch64 is supported. Signed-off-by: Leif Lindholm <leif.lindholm(a)linaro.org> --- generate/efi/AcpiPkg.dsc | 2 +- generate/efi/README | 1 + generate/efi/acpidump/acpidump.inf | 6 ++---- source/include/platform/acefi.h | 2 +- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/generate/efi/AcpiPkg.dsc b/generate/efi/AcpiPkg.dsc index 323d39c..9302555 100644 --- a/generate/efi/AcpiPkg.dsc +++ b/generate/efi/AcpiPkg.dsc @@ -18,7 +18,7 @@ PLATFORM_VERSION = 1.0 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/Acpi - SUPPORTED_ARCHITECTURES = IA32|X64 + SUPPORTED_ARCHITECTURES = AARCH64|IA32|X64 BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT diff --git a/generate/efi/README b/generate/efi/README index 7550e9d..b3ec3ff 100644 --- a/generate/efi/README +++ b/generate/efi/README @@ -20,6 +20,7 @@ But the porting has only been tested in a Linux environment. You can find built EFI binaries (e.x., acpidump.efi) in the following folders: + Build/Acpi/DEBUG_GCC47/AARCH64: aarch64 targets Build/Acpi/DEBUG_GCC47/IA32: i386 targets Build/Acpi/DEBUG_GCC47/X64: x86_64 targets diff --git a/generate/efi/acpidump/acpidump.inf b/generate/efi/acpidump/acpidump.inf index 8d2c979..e5f21c0 100644 --- a/generate/efi/acpidump/acpidump.inf +++ b/generate/efi/acpidump/acpidump.inf @@ -55,7 +55,5 @@ BaseLib [BuildOptions] - MSFT:*_*_IA32_CC_FLAGS = /Oi- /WX- /D_EDK2_EFI /DACPI_DUMP_APP - MSFT:*_*_X64_CC_FLAGS = /Oi- /WX- /D_EDK2_EFI /DACPI_DUMP_APP - GCC:*_*_IA32_CC_FLAGS = -U__linux__ -U_LINUX -D_EDK2_EFI -DACPI_DUMP_APP -fno-builtin -iwithprefix include - GCC:*_*_X64_CC_FLAGS = -U__linux__ -U_LINUX -D_EDK2_EFI -DACPI_DUMP_APP -fno-builtin -iwithprefix include + MSFT:*_*_*_CC_FLAGS = /Oi- /WX- /D_EDK2_EFI /DACPI_DUMP_APP + GCC:*_*_*_CC_FLAGS = -U__linux__ -U_LINUX -D_EDK2_EFI -DACPI_DUMP_APP -fno-builtin -iwithprefix include diff --git a/source/include/platform/acefi.h b/source/include/platform/acefi.h index dfa4894..30a5429 100644 --- a/source/include/platform/acefi.h +++ b/source/include/platform/acefi.h @@ -140,7 +140,7 @@ #define VOID void -#if defined(__ia64__) || defined(__x86_64__) +#if defined(__aarch64__) || (__ia64__) || defined(__x86_64__) #define ACPI_MACHINE_WIDTH 64 -- 2.10.2

8 years

[PATCH v4 0/3] add hikey platform

by Haojian Zhuang

v4: 1. Add bit definition of MDDRC_AXI_MAP register. 2. Clean patches with comments. v3: 1. Clean patches with comments. v2: 1. Fix UniApp in hikey DSC file. v1: 1. Add hikey platform with DwEmmc Driver. Haojian Zhuang (3): Platforms: add skeleton of hikey platform Drivers/Mmc/DwEmmc: add designware emmc support Platforms/Hisilicon/HiKey: enable emmc Chips/Hisilicon/Hi6220/Hi6220.dec | 32 + Chips/Hisilicon/Hi6220/Include/Hi6220.h | 83 +++ Drivers/Mmc/DwEmmcDxe/DwEmmc.h | 127 ++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c | 648 +++++++++++++++++++++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec | 42 ++ Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf | 55 ++ Platforms/Hisilicon/HiKey/HiKey.dec | 36 ++ Platforms/Hisilicon/HiKey/HiKey.dsc | 489 ++++++++++++++++ Platforms/Hisilicon/HiKey/HiKey.fdf | 351 +++++++++++ Platforms/Hisilicon/HiKey/Include/ArmPlatform.h | 26 + Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c | 159 +++++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S | 49 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf | 51 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c | 235 ++++++++ 14 files changed, 2383 insertions(+) create mode 100644 Chips/Hisilicon/Hi6220/Hi6220.dec create mode 100644 Chips/Hisilicon/Hi6220/Include/Hi6220.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmc.h create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.c create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.dec create mode 100644 Drivers/Mmc/DwEmmcDxe/DwEmmcDxe.inf create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dec create mode 100644 Platforms/Hisilicon/HiKey/HiKey.dsc create mode 100644 Platforms/Hisilicon/HiKey/HiKey.fdf create mode 100644 Platforms/Hisilicon/HiKey/Include/ArmPlatform.h create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf create mode 100644 Platforms/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c -- 2.7.4

8 years

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