On 27 October 2016 at 08:46, Bhupesh Sharma bhupesh.sharma@nxp.com wrote:
Hi Ard,
Please see my replies inline.
From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Tuesday, October 18, 2016 2:46 PM
On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:
From: Sakar Arora sakar.arora@nxp.com
This patch adds the basic support for NXP/FSL's LS1043A RDB board. LS1043A RDB board supports a number of on-board peripherals. This patch adds the basic framework for the same.
Further details about this board can be seen here: http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/qoriq-arm-processors/qoriq-ls1043a-reference-design-
boa
rd:LS1043A-RDB
Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com
[...]
diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c new file mode 100644 index 0000000..ef93623 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c @@ -0,0 +1,149 @@ +/** LS1043aRdbMem.c +* +* RDB memory specific Library for LS1043A SoC. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights
reserved.
+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the license +may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS
OR IMPLIED.
+* +**/
+#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h>
+#include <Library/PlatformLib.h>
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+/**
- Return the Virtual Memory Map of your platform
- This Virtual Memory Map is used by MemoryInitPei Module to
initialize the MMU on your platform.
- @param[out] VirtualMemoryMap Array of
ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. Thisarray must be ended by a zero-filled
entry+**/ +VOID +ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
- )
+{
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
- UINTN Index = 0;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- ASSERT(VirtualMemoryMap != NULL);
- VirtualMemoryTable =
- (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES
- (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) *
- MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
- if (VirtualMemoryTable == NULL) {
- return;
- }
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
- CacheAttributes = DDR_ATTRIBUTES_CACHED; } else {
- CacheAttributes = DDR_ATTRIBUTES_UNCACHED; }
- // DRAM1 (Must be 1st entry)
Why? Because the regions overlap? If so, please document that more explicitly.
No the DRAM regions do no overlap. But I noticed crashes in DXE phase if this is not the first entry.
I guess this first entry is passed via PEIM to DXE where the overall memory region availability is conveyed to DXE.
No, this is not the case. If you are seeing crashes dependent on the ordering here, and the regions do not overlap, you may have uncovered a bug in the page table code, and we'd like to know about it.
- VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_BASE_ADDR;
- VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // CCSR Space
- VirtualMemoryTable[++Index].PhysicalBase = LS1043A_CCSR_BASE_ADDR;
- VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
- // OCRAM1 Space
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_OCRAM1_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase =
LS1043A_OCRAM1_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_OCRAM1_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // OCRAM2 Space
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_OCRAM2_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase =
LS1043A_OCRAM2_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_OCRAM2_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // IFC region 1
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_IFC_REGION1_BASE_ADDR;
VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION1_BASE_ADDR;
- VirtualMemoryTable[Index].Length =
LS1043A_IFC_REGION1_BASE_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
- // QMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_QMAN_SWP_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase
= LS1043A_QMAN_SWP_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_QMAN_SWP_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
- // BMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_BMAN_SWP_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase
= LS1043A_BMAN_SWP_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_BMAN_SWP_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
- // IFC region 2
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_IFC_REGION2_BASE_ADDR;
VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION2_BASE_ADDR;
- VirtualMemoryTable[Index].Length =
LS1043A_IFC_REGION2_BASE_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // DRAM2
- VirtualMemoryTable[++Index].PhysicalBase =
LS1043A_DRAM2_BASE_ADDR;
- VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM2_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_DRAM2_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // PCIe1
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_PCI_EXP1_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase
= LS1043A_PCI_EXP1_BASE_ADDR;
- VirtualMemoryTable[Index].Length =
LS1043A_PCI_EXP1_BASE_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
- // PCIe2
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_PCI_EXP2_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase
= LS1043A_PCI_EXP2_BASE_ADDR;
- VirtualMemoryTable[Index].Length =
LS1043A_PCI_EXP2_BASE_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
- // PCIe3
- VirtualMemoryTable[++Index].PhysicalBase =
- LS1043A_PCI_EXP3_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase
= LS1043A_PCI_EXP3_BASE_ADDR;
- VirtualMemoryTable[Index].Length =
LS1043A_PCI_EXP3_BASE_SIZE;
- VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
- // DRAM3
- VirtualMemoryTable[++Index].PhysicalBase =
LS1043A_DRAM3_BASE_ADDR;
- VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM3_BASE_ADDR;
- VirtualMemoryTable[Index].Length = LS1043A_DRAM3_SIZE;
- VirtualMemoryTable[Index].Attributes = CacheAttributes;
- // End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
- VirtualMemoryTable[Index].VirtualBase = 0;
- VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes =
(ARM_MEMORY_REGION_ATTRIBUTES)0;
- ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
- *VirtualMemoryMap = VirtualMemoryTable; }
-- 1.9.1
Regards, Bhupesh