On Tue, Oct 18, 2016 at 10:15:41AM +0100, Ard Biesheuvel wrote:

...

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf new file mode 100644 index 0000000..e09d940 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf @@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = LS1043aRdbLib
• FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b

Please use a fresh GUID here

For example using https://www.guidgenerator.com/online-guid-generator.aspx

It's important to use a generator that follows rfc 4122 (with the tweaks that make them GUIDs rather then UUIDs) in order to maintain the statistical uniqueness.

All kinds of things can go horribly wrong if GUIDs clash, whether it be in .inf, .dec or .c/.h files...

Regards,

Leif

Hi Ard,

Please see my replies inline.

From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Tuesday, October 18, 2016 2:46 PM

On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:

...

From: Sakar Arora sakar.arora@nxp.com

This patch adds the basic support for NXP/FSL's LS1043A RDB board. LS1043A RDB board supports a number of on-board peripherals. This patch adds the basic framework for the same.

Further details about this board can be seen here: http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/qoriq-arm-processors/qoriq-ls1043a-reference-design-

boa

...

rd:LS1043A-RDB

Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com

---

Platforms/Nxp/LS1043aRdb/Include/Library/Common.h | 68 ++++++++ .../Nxp/LS1043aRdb/Include/Library/PlatformLib.h | 178

+++++++++++++++++++++

...

.../Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c | 103

++++++++++++

...

.../LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c | 107

+++++++++++++

...

.../Library/LS1043aRdbLib/LS1043aRdbHelper.S | 61 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbLib.inf | 56 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbMem.c | 149

+++++++++++++++++

...

7 files changed, 722 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Common.h create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h new file mode 100644 index 0000000..192a249 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h @@ -0,0 +1,68 @@ +/** @Common.h

• Header defining the General Purpose Utilities
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

• This program and the accompanying materials are licensed and made
• available under the terms and conditions of the BSD License which
• accompanies this distribution. The full text of the license may be
• found at http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
• BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+**/

+#ifndef __COMMON_H__ +#define __COMMON_H__

+#define DMA_MINALIGN 64

+#define offsetof(TYPE, MEMBER) ((UINTN) &((TYPE *)0)->MEMBER)

+typedef UINTN PhysAddrT; +typedef UINTN PhysSizeT;

+static inline PhysAddrT VirtToPhys(VOID * VAddr) {

•   return (PhysAddrT)(VAddr);
  

+}

+/*

• • The ALLOC_CACHE_ALIGN_BUF macro is used to allocate a buffer
• • that meets the minimum architecture alignment requirements for

DMA.

...

• • The resulting buffer is aligned to the value of DMA_MINALIGN.
• • The buffer variable created is a pointer to the specified type,

+and

• • NOT an array.
• • The size parameter is the number of array elements to allocate.
• */

+#define ALIGN_BUFF(x,a) ALIGN_MSK((x),(typeof(x))(a)-1) +#define ALIGN_MSK(x,mask) (((x)+(mask))&~(mask))

+#define PAD_CNT(S, Pad) (((S) - 1) / (Pad) + 1) #define PAD_SIZE(S, +Pad) (PAD_CNT(S, Pad) * Pad)

+#define ROUND_OFF(a,b) (((a) + (b) - 1) & ~((b) - 1))

+#define DMA_MINALIGN 64

+#define ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, Pad)

\

...

•   INT8 __##Name[ROUND_OFF(PAD_SIZE((Size) * sizeof(Type), Pad),
  

Align) \

...

•                 + (Align - 1)];
  

\

...

\

...

•   Type *Name = (Type *) ALIGN_BUFF((UINTN)__##Name, Align)
  

+#define ALLOC_ALIGN_BUF(Type, Name, Size, Align) \

•   ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, 1)
  

+#define ALLOC_CACHE_ALIGN_BUF_PAD(Type, Name, Size, Pad)

\

...

•   ALLOC_ALIGN_BUF_PAD(Type, Name, size, DMA_MINALIGN, Pad)
  

+#define ALLOC_CACHE_ALIGN_BUF(Type, Name, Size)

\

...

•   ALLOC_ALIGN_BUF(Type, Name, Size, DMA_MINALIGN)
  

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h new file mode 100644 index 0000000..39247e8 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h @@ -0,0 +1,178 @@ +/** LS1043aRdb.h +* Header defining the LS1043aRdb constants (Base addresses, sizes, +flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the

license

...

+may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS

OR IMPLIED.

...

+* +**/

+#ifndef __LS1043aRDB_PLATFORM_H__ +#define __LS1043aRDB_PLATFORM_H__

+// Types +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))

+// DDR attributes +#define DDR_ATTRIBUTES_CACHED

ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK

...

+#define DDR_ATTRIBUTES_UNCACHED

ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

...

+#define LS1043A_CACHELINE_SIZE 32

+#define LS1043A_SECURE_BOOTROM_BASE_ADDR 0x00000000 +#define LS1043A_SECURE_BOOTROM_SIZE 0x00100000 /* 1MB */ +#define LS1043A_EXT_BOOTROM_BASE_ADDR 0x00100000 +#define LS1043A_EXT_BOOTROM_SIZE 0x00F00000 /*

15MB */

...

+#define LS1043A_CCSR_BASE_ADDR 0x01000000 +#define LS1043A_CCSR_SIZE 0x0F000000 /* 240MB

*/

...

•   #define LS1043A_IMMR                    0x01000000
  

•   #define LS1043A_DDR_ADDR                0x01080000
  

•   #define LS1043A_DSPI_ADDR       0x02100000
  

•   #define LS1043A_SDXC_ADDR       0x01560000
  

•   #define LS1043A_CCI400_ADDR             (LS1043A_IMMR +
  

0x00180000)

...

•   #define LS1043A_TZASC380_ADDR   (LS1043A_IMMR + 0x00500000)
  

•   #define LS1043A_CSU_ADDR                (LS1043A_IMMR +
  

0x00510000)

...

•   #define LS1043A_GUTS_ADDR       (LS1043A_IMMR + 0x00ee0000)
  

•   #define LS1043A_CLK_ADDR                (LS1043A_IMMR +
  

0x00ee1000)

...

•   #define LS1043A_FMAN_ADDR       (LS1043A_IMMR + 0x00a00000)
  

•   #define LS1043A_BMAN_ADDR        (LS1043A_IMMR + 0x00890000)
  

•   #define LS1043A_QMAN_ADDR        (LS1043A_IMMR + 0x00880000)
  

•   #define GIC_BASE_ADDR                   0x01402000
  

•   #define GIC_SIZE                        0x1000
  

•   #define GICDIST_BASE_ADDR               0x01401000
  

•   #define GICDIST_SIZE                    0x1000
  

•   #define DUART1_BASE_ADDR                0x21C0000
  

•   #define DUART1_SIZE                     0x1000
  

•   #define DUART2_BASE_ADDR                0x21D0000
  

•   #define DUART2_SIZE                     0x1000
  

•   #define WDOG1_BASE_ADDR                 0x02AD0000
  

•   #define WDOG2_BASE_ADDR                 0x02AE0000
  

•   #define WDOG3_BASE_ADDR                 0x02A70000
  

•   #define WDOG4_BASE_ADDR                 0x02A80000
  

•   #define WDOG5_BASE_ADDR                 0x02A90000
  

•   #define WDOG_SIZE                       0x1000
  

•           #define WDOG_WCR_OFFSET         0
  

•           #define WDOG_WSR_OFFSET         2
  

•           #define WDOG_WRSR_OFFSET        4
  

•           #define WDOG_WICR_OFFSET        6
  

•           #define WDOG_WCR_WT             (0xFF << 8)
  

•           #define WDOG_WCR_WDE            (1 << 2)
  

•           #define WDOG_SERVICE_SEQ1       0x5555
  

•           #define WDOG_SERVICE_SEQ2       0xAAAA
  

•   #define WDOG_WCR_WDZST  0x1
  

•   #define WDOG_WCR_WRE (1 << 3)  /* -> WDOG Reset Enable */
  

•   #define I2C0_BASE_ADDRESS               0x02180000
  

•   #define I2C1_BASE_ADDRESS               0x02190000
  

•   #define I2C2_BASE_ADDRESS               0x021A0000
  

•   #define I2C3_BASE_ADDRESS               0x02183000
  

•   #define I2C_SIZE                        0x10000
  

•   #define DSPI_MEMORY_SIZE                0x10000
  

•   #define DDRC_MEMORY_SIZE                0x10000
  

•   #define SDXC_MEMORY_SIZE                0x10000
  

•   #define LS1043A_TIMER_ADDR      0x02b00000
  

•   #define IFC_REG_BASE_ADDR          0x1530000
  

•   #define IFC_REG_SIZE               0x0003000
  

•   #define SCFG_BASE_ADDR             0x1570000
  

•   #define SCFG_SIZE                  0x0010000
  

+/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)

+#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 +#define IDR1_PAGESIZE_MASK 0x80000000

+#define LS1043A_OCRAM1_BASE_ADDR 0x10000000 +#define LS1043A_OCRAM1_SIZE 0x00010000 /* 64KB */ +#define LS1043A_OCRAM2_BASE_ADDR 0x10010000 +#define LS1043A_OCRAM2_SIZE 0x00010000 /* 64KB */ +#define LS1043A_STM_BASE_ADDR 0x12000000 +#define LS1043A_STM_SIZE 0x01000000 /*

16MB */

...

+#define LS1043A_DCSR_BASE_ADDR 0x20000000 +#define LS1043A_DCSR_SIZE 0x04000000 /* 64MB */ +#define LS1043A_QSPI_BASE_ADDR 0x40000000 +#define LS1043A_QSPI_SIZE 0x20000000 /* 512MB

*/

...

+#define LS1043A_IFC_REGION1_BASE_ADDR 0x60000000 +#define LS1043A_IFC_REGION1_BASE_SIZE 0x20000000 /* 512MB

*/

...

+#define LS1043A_DRAM1_BASE_ADDR 0x0080000000 +#define LS1043A_DRAM1_SIZE 0x0080000000 /* 2GB

*/

...

+#define LS1043A_QMAN_SWP_BASE_ADDR 0x0500000000 +#define LS1043A_QMAN_SWP_SIZE 0x0080000000 /* 128MB

*/

...

+#define LS1043A_BMAN_SWP_BASE_ADDR 0x0508000000 +#define LS1043A_BMAN_SWP_SIZE 0x0080000000 /* 128MB

*/

...

+#define LS1043A_IFC_REGION2_BASE_ADDR 0x0620000000 +#define LS1043A_IFC_REGION2_BASE_SIZE 0x00E0000000 /* 3.5GB

*/

...

+#define LS1043A_DRAM2_BASE_ADDR 0x0880000000 +#define LS1043A_DRAM2_SIZE 0x0780000000 /* 30GB

*/

...

+#define LS1043A_SERDES_ADDR (LS1043A_IMMR +

0xEA0000)

...

+#define LS1043A_SRDS_1 +#define LS1043A_PCI_EXP1_BASE_ADDR 0x4000000000 +#define LS1043A_PCI_EXP1_BASE_SIZE 0x800000000 /* 32GB

*/

...

+#define LS1043A_PCI_EXP2_BASE_ADDR 0x4800000000 +#define LS1043A_PCI_EXP2_BASE_SIZE 0x800000000 /* 32GB

*/

...

+#define LS1043A_PCI_EXP3_BASE_ADDR 0x5000000000 +#define LS1043A_PCI_EXP3_BASE_SIZE 0x800000000 /* 32GB

*/

...

+#define LS1043A_DRAM3_BASE_ADDR 0x8800000000 +#define LS1043A_DRAM3_SIZE 0x7800000000 /* 480GB

*/

...

+/*

• • CPLD
• */

+#define LS1043A_CPLD_BASE 0x7fb00000

+/*

• • Global defines
• */

+#define NOR_BOOT 0x0 +#define NAND_BOOT 0x1 +#define SD_BOOT 0x2

+/* PCI controllers addresses */ +#define LS1043A_PCIE1_PHYS_BASE 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_BASE 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_BASE 0x5000000000ULL

+#define LS1043A_PCIE1_PHYS_ADDR 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_ADDR 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_ADDR 0x5000000000ULL

+#define LS1043A_PCIE1_ADDR 0x03600000 +#define LS1043A_PCIE2_ADDR 0x03500000 +#define LS1043A_PCIE3_ADDR 0x03600000

+/* PCIe */ +#define LS1043A_LS_PCI /* Enable PCI/PCIE */ +#define LS1043A_LS_PCIE1 /* PCIE controler 1 */ +#define LS1043A_LS_PCIE2 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE3 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE_LAYERSCAPE /* Use common FSL Layerscape

PCIe

...

+code */

+#define LS1043A_LS_PCI_64BIT

+#define LS1043A_LS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define LS1043A_LS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define LS1043A_LS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define LS1043A_LS_PCIE_CFG1_SIZE 0x00001000 /* 4k */

+#define LS1043A_LS_PCIE_IO_BUS 0x00000000 +#define LS1043A_LS_PCIE_IO_PHYS_OFF 0x00010000 +#define LS1043A_LS_PCIE_IO_SIZE 0x00010000 /* 64k */

+#define LS1043A_LS_PCIE_MEM_BUS 0x40000000 +#define LS1043A_LS_PCIE_MEM_PHYS_OFF 0x40000000 +#define LS1043A_LS_PCIE_MEM_SIZE 0x40000000 /* 1 GB */

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c new file mode 100644 index 0000000..7159749 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c @@ -0,0 +1,103 @@ +/** Common.c +* +* Copyright (c) 2016, Freescale Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the

license

...

+may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS

OR IMPLIED.

...

+* +**/

+#include <Library/PlatformLib.h> +#include <Library/DebugLib.h>

+UINT32 +__Div64_32 (

• IN UINT64 *N,
• IN UINT32 Base
• )

+{

• UINT64 Rem = *N;
• UINT64 b = Base;
• UINT64 Res, d = 1;
• UINT32 High = Rem >> 32;
• /** Reduce the thing a bit first */ Res = 0; if (High >= Base) {
• High /= Base;
• Res = (UINT64) High << 32;
• Rem -= (UINT64) (High*Base) << 32; }
• while ((UINTN)b > 0 && b < Rem) {
• b = b+b;
• d = d+d;
• }
• do {
• if (Rem >= b) {

•  Rem -= b;
  

•  Res += d;
  

• }
• b >>= 1;
• d >>= 1;
• } while (d);
• *N = Res;
• return Rem;

+}

Why do we need this?

...

+/*

• • PrINT32 Sizes As "Xxx KiB", "Xxx.Y KiB", "Xxx MiB", "Xxx.Y MiB",
• • Xxx GiB, Xxx.Y GiB, Etc As Needed; Allow for Optional Trailing

+String

• • (Like "\n")
• */

+VOID +PrintSize (

• IN UINT64 Size,
• IN CONST INT8 *S
• )

+{

• UINT64 M = 0, N;
• UINT64 F;
• static CONST INT8 Names[] = {'E', 'P', 'T', 'G', 'M', 'K'};
• UINT64 D = 10 * ARRAY_SIZE(Names);
• CHAR8 C = 0;
• UINT32 I;
• for (I = 0; I < ARRAY_SIZE(Names); I++, D -= 10) {
• if (Size >> D) {

•  C = Names[I];
  

•  break;
  

• }
• }
• if (!C) {
• DEBUG((EFI_D_ERROR, "%Ld Bytes,\n %a", Size, S));
• return;
• }
• N = Size >> D;
• F = Size & ((1ULL << D) - 1);
• /* if There'S A Remainder, Deal With It */ if (F) {
• M = (10ULL * F + (1ULL << (D - 1))) >> D;
• if (M >= 10) {

•       M -= 10;
  

•       N += 1;
  

• }
• }
• DEBUG((EFI_D_ERROR, "%Ld", N));
• if (M) {
• DEBUG((EFI_D_ERROR, ".%Ld", M));
• }
• DEBUG((EFI_D_ERROR, " %ciB, %a ", C, S)); }

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c new file mode 100644 index 0000000..4fcb8a3 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c @@ -0,0 +1,107 @@ +/** LS1043aRdb.c +* +* RDB specific Library for LS1043A SoC, containing functions to +initialize +* RDB boards. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the

license

...

+may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS

OR IMPLIED.

...

+* +**/

+#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Ppi/ArmMpCoreInfo.h> +#include <Library/PlatformLib.h>

+/**

• Return the current Boot Mode
• This function returns the boot reason on the platform

+**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode (

• VOID
• )

+{

• return BOOT_WITH_FULL_CONFIGURATION; }

+/**

• Placeholder for Platform Initialization **/ RETURN_STATUS

+ArmPlatformInitialize (

• IN UINTN MpId
• )

+{

• return RETURN_SUCCESS;

+}

+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {

• {
• // Cluster 0, Core 0
• 0x0, 0x0,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (EFI_PHYSICAL_ADDRESS)0,
• (EFI_PHYSICAL_ADDRESS)0,
• (EFI_PHYSICAL_ADDRESS)0,
• (UINT64)0xFFFFFFFF
• },

+};

+EFI_STATUS +PrePeiCoreGetMpCoreInfo (

• OUT UINTN *CoreCount,
• OUT ARM_CORE_INFO **ArmCoreTable
• )

+{

• *CoreCount = sizeof(LS1043aMpCoreInfoCTA53x4) /

sizeof(ARM_CORE_INFO);

...

• *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
• return EFI_SUCCESS;

+}

+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid +is undefined in the contect of PrePeiCore

This is not true, and has been fixed upstream. You simply need to add gArmMpCoreInfoPpiGuid to the [Guids] section of the .inf

Ok, will change this in v2.

...

+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;' +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };

+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {

• {
• EFI_PEI_PPI_DESCRIPTOR_PPI,
• &mArmMpCoreInfoPpiGuid,
• &mMpCoreInfoPpi
• }

+};

+VOID +ArmPlatformGetPlatformPpiList (

• OUT UINTN *PpiListSize,
• OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
• )

+{

• *PpiListSize = sizeof(gPlatformPpiTable);
• *PpiList = gPlatformPpiTable;

+}

+UINTN +ArmPlatformGetCorePosition (

• IN UINTN MpId
• )

+{

• return 1;

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S new file mode 100644 index 0000000..5d9807f --- /dev/null +++

b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.

...

+++ S @@ -0,0 +1,61 @@ +# @file +# +# Based on

BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S

...

+# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

+# +# This program and the accompanying materials # are licensed and +made available under the terms and conditions of the BSD License # +which accompanies this distribution. The full text of the license +may be found at # http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+# +#

+#include <AsmMacroIoLib.h> +#include <AsmMacroIoLibV8.h> +#include <AutoGen.h>

+.text +.align 2

+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)

+GCC_ASM_IMPORT(ArmReadMpidr)

+//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore):

•   and x1, x0, #3
  

•   mov     x0, #0
  

• cbnz x1, 1f

•   mov x0, #1
  

+1:

• ret

How about

tst x0, #3 cset x0, eq ret

Ok.

...

+ASM_PFX(ArmPlatformPeiBootAction): +EL1_OR_EL2_OR_EL3(x0) +1: +2:

•   ret
  

+3:

•   LoadConstantToReg(FixedPcdGet32(PcdCounterFrequency), x0)
  

Please don't use LoadConstantToReg(), you can use MOV32() or MOV64 instead.

Ok.

...

•   msr cntfrq_el0, x0
  

•   ret
  

+//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):

• LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), x0)
• ldrh w0, [x0]

Same here. FixedPcdGet32(PcdArmPrimaryCore) resolves to a literal constant, no need for the ldr

Ok.

...

• ret

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf new file mode 100644 index 0000000..e09d940 --- /dev/null +++

b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf

...

@@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

+# +# This program and the accompanying materials # are licensed and +made available under the terms and conditions of the BSD License # +which accompanies this distribution. The full text of the license +may be found at # http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+# +#*/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = LS1043aRdbLib
• FILE_GUID = 736343a0-1d96-11e0-aaaa-

0002a5d5c51b

Please use a fresh GUID here

Ok.

...

• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = ArmPlatformLib

+[Packages]

• MdePkg/MdePkg.dec
• MdeModulePkg/MdeModulePkg.dec
• EmbeddedPkg/EmbeddedPkg.dec
• ArmPkg/ArmPkg.dec
• ArmPlatformPkg/ArmPlatformPkg.dec
• OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec

+[LibraryClasses]

• IoLib
• ArmLib
• MemoryAllocationLib
• I2cLib
• DdrLib
• SocLib

+[Sources.common]

• LS1043aRdbHelper.S | GCC
• LS1043aRdb.c
• LS1043aRdbMem.c
• Common.c

+[FeaturePcd]

• gEmbeddedTokenSpaceGuid.PcdCacheEnable

+[FixedPcd]

• gArmTokenSpaceGuid.PcdArmPrimaryCore
• gArmTokenSpaceGuid.PcdFdBaseAddress
• gArmTokenSpaceGuid.PcdFdSize
• gArmTokenSpaceGuid.PcdSystemMemoryBase
• gArmTokenSpaceGuid.PcdSystemMemorySize
• gArmPlatformTokenSpaceGuid.PcdCounterFrequency

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c new file mode 100644 index 0000000..ef93623 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c @@ -0,0 +1,149 @@ +/** LS1043aRdbMem.c +* +* RDB memory specific Library for LS1043A SoC. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

+* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of +the BSD License +* which accompanies this distribution. The full text of the license +may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS

OR IMPLIED.

...

+* +**/

+#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h>

+#include <Library/PlatformLib.h>

+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25

+/**

• Return the Virtual Memory Map of your platform
• This Virtual Memory Map is used by MemoryInitPei Module to

initialize the MMU on your platform.

...

• @param[out] VirtualMemoryMap Array of

ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-

...

•                                Virtual Memory mapping. This
  

array must be ended by a zero-filled

...

•                                entry
  

+**/ +VOID +ArmPlatformGetVirtualMemoryMap (

• IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
• )

+{

• ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
• UINTN Index = 0;
• ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
• ASSERT(VirtualMemoryMap != NULL);
• VirtualMemoryTable =
• (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES
• (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) *
• MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
• if (VirtualMemoryTable == NULL) {
• return;
• }
• if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
• CacheAttributes = DDR_ATTRIBUTES_CACHED; } else {
• CacheAttributes = DDR_ATTRIBUTES_UNCACHED; }
• // DRAM1 (Must be 1st entry)

Why? Because the regions overlap? If so, please document that more explicitly.

No the DRAM regions do no overlap. But I noticed crashes in DXE phase if this is not the first entry.

I guess this first entry is passed via PEIM to DXE where the overall memory region availability is conveyed to DXE.

...

• VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // CCSR Space
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_CCSR_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

...

• // OCRAM1 Space
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_OCRAM1_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase =

LS1043A_OCRAM1_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length = LS1043A_OCRAM1_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // OCRAM2 Space
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_OCRAM2_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase =

LS1043A_OCRAM2_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length = LS1043A_OCRAM2_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // IFC region 1
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_IFC_REGION1_BASE_ADDR;

VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION1_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length =

LS1043A_IFC_REGION1_BASE_SIZE;

...

• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

...

• // QMAN SWP
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_QMAN_SWP_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase

= LS1043A_QMAN_SWP_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length = LS1043A_QMAN_SWP_SIZE;
• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

...

• // BMAN SWP
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_BMAN_SWP_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase

= LS1043A_BMAN_SWP_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length = LS1043A_BMAN_SWP_SIZE;
• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;

...

• // IFC region 2
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_IFC_REGION2_BASE_ADDR;

VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION2_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length =

LS1043A_IFC_REGION2_BASE_SIZE;

...

• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // DRAM2
• VirtualMemoryTable[++Index].PhysicalBase =

LS1043A_DRAM2_BASE_ADDR;

...

• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM2_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM2_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // PCIe1
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_PCI_EXP1_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase

= LS1043A_PCI_EXP1_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length =

LS1043A_PCI_EXP1_BASE_SIZE;

...

• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

...

• // PCIe2
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_PCI_EXP2_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase

= LS1043A_PCI_EXP2_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length =

LS1043A_PCI_EXP2_BASE_SIZE;

...

• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

...

• // PCIe3
• VirtualMemoryTable[++Index].PhysicalBase =
• LS1043A_PCI_EXP3_BASE_ADDR; VirtualMemoryTable[Index].VirtualBase

= LS1043A_PCI_EXP3_BASE_ADDR;

...

• VirtualMemoryTable[Index].Length =

LS1043A_PCI_EXP3_BASE_SIZE;

...

• VirtualMemoryTable[Index].Attributes =

ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

...

• // DRAM3
• VirtualMemoryTable[++Index].PhysicalBase =

LS1043A_DRAM3_BASE_ADDR;

...

• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM3_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM3_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // End of Table
• VirtualMemoryTable[++Index].PhysicalBase = 0;
• VirtualMemoryTable[Index].VirtualBase = 0;
• VirtualMemoryTable[Index].Length = 0;
• VirtualMemoryTable[Index].Attributes =

(ARM_MEMORY_REGION_ATTRIBUTES)0;

...

• ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
• *VirtualMemoryMap = VirtualMemoryTable; }

-- 1.9.1

Regards, Bhupesh

Generic comment - there are quite a few tabs interspersed in the below. Apart from going against the coding style, it does not appear intentional (as freely mixed). BaseTools/Scripts/PatchCheck.py can help weed out minor formatting issues like this.

On Tue, Oct 18, 2016 at 01:34:00AM +0530, Bhupesh Sharma wrote:

From: Sakar Arora sakar.arora@nxp.com

This patch adds the basic support for NXP/FSL's LS1043A RDB board. LS1043A RDB board supports a number of on-board peripherals. This patch adds the basic framework for the same.

Further details about this board can be seen here: http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/qoriq-arm-processors/qoriq-ls1043a-reference-design-board:LS1043A-RDB

Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com

---

Platforms/Nxp/LS1043aRdb/Include/Library/Common.h | 68 ++++++++ .../Nxp/LS1043aRdb/Include/Library/PlatformLib.h | 178 +++++++++++++++++++++ .../Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c | 103 ++++++++++++ .../LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c | 107 +++++++++++++ .../Library/LS1043aRdbLib/LS1043aRdbHelper.S | 61 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbLib.inf | 56 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbMem.c | 149 +++++++++++++++++ 7 files changed, 722 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Common.h create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h new file mode 100644 index 0000000..192a249 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h @@ -0,0 +1,68 @@ +/** @Common.h

• Header defining the General Purpose Utilities
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#ifndef __COMMON_H__ +#define __COMMON_H__

Feels like a very "common" name ... add the LS1043aRDB prefix like in later files?

+#define DMA_MINALIGN 64

+#define offsetof(TYPE, MEMBER) ((UINTN) &((TYPE *)0)->MEMBER)

+typedef UINTN PhysAddrT; +typedef UINTN PhysSizeT;

+static inline PhysAddrT VirtToPhys(VOID * VAddr) +{

•   return (PhysAddrT)(VAddr);
  

+}

+/*

• • The ALLOC_CACHE_ALIGN_BUF macro is used to allocate a buffer
• • that meets the minimum architecture alignment requirements for DMA.
• • The resulting buffer is aligned to the value of DMA_MINALIGN.
• • The buffer variable created is a pointer to the specified type, and
• • NOT an array.
• • The size parameter is the number of array elements to allocate.
• */

+#define ALIGN_BUFF(x,a) ALIGN_MSK((x),(typeof(x))(a)-1)

BUFF here, BUF later on.

+#define ALIGN_MSK(x,mask) (((x)+(mask))&~(mask))

+#define PAD_CNT(S, Pad) (((S) - 1) / (Pad) + 1) +#define PAD_SIZE(S, Pad) (PAD_CNT(S, Pad) * Pad)

+#define ROUND_OFF(a,b) (((a) + (b) - 1) & ~((b) - 1))

+#define DMA_MINALIGN 64

+#define ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, Pad) \

• INT8 __##Name[ROUND_OFF(PAD_SIZE((Size) * sizeof(Type), Pad), Align) \

•       + (Align - 1)];					\
  

• 							\
  

• Type *Name = (Type *) ALIGN_BUFF((UINTN)__##Name, Align)

+#define ALLOC_ALIGN_BUF(Type, Name, Size, Align) \

• ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, 1)

+#define ALLOC_CACHE_ALIGN_BUF_PAD(Type, Name, Size, Pad) \

• ALLOC_ALIGN_BUF_PAD(Type, Name, size, DMA_MINALIGN, Pad)

+#define ALLOC_CACHE_ALIGN_BUF(Type, Name, Size) \

• ALLOC_ALIGN_BUF(Type, Name, Size, DMA_MINALIGN)

+#endif

So, a generic comment/question on this file: It looks much like the kind of header used to glue a piece of OS-independent code into a specific codebase. Is this what is being done here? If so, a bit more leeway can be given in the interest of simplifying future updates from new OS-independent releases.

Otherwise, much of what is defined in this Common.h could be replaced with already-existing macros/helpers.

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h new file mode 100644 index 0000000..39247e8 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h @@ -0,0 +1,178 @@ +/** LS1043aRdb.h +* Header defining the LS1043aRdb constants (Base addresses, sizes, flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __LS1043aRDB_PLATFORM_H__ +#define __LS1043aRDB_PLATFORM_H__

+// Types +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))

+// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

+#define LS1043A_CACHELINE_SIZE 32

+#define LS1043A_SECURE_BOOTROM_BASE_ADDR 0x00000000 +#define LS1043A_SECURE_BOOTROM_SIZE 0x00100000 /* 1MB */

Could use SIZE_1M (and x * SIZE_1M below).

+#define LS1043A_EXT_BOOTROM_BASE_ADDR 0x00100000 +#define LS1043A_EXT_BOOTROM_SIZE 0x00F00000 /* 15MB */ +#define LS1043A_CCSR_BASE_ADDR 0x01000000 +#define LS1043A_CCSR_SIZE 0x0F000000 /* 240MB */

• #define LS1043A_IMMR 0x01000000
• #define LS1043A_DDR_ADDR 0x01080000
• #define LS1043A_DSPI_ADDR 0x02100000
• #define LS1043A_SDXC_ADDR 0x01560000
• #define LS1043A_CCI400_ADDR (LS1043A_IMMR + 0x00180000)
• #define LS1043A_TZASC380_ADDR (LS1043A_IMMR + 0x00500000)
• #define LS1043A_CSU_ADDR (LS1043A_IMMR + 0x00510000)
• #define LS1043A_GUTS_ADDR (LS1043A_IMMR + 0x00ee0000)
• #define LS1043A_CLK_ADDR (LS1043A_IMMR + 0x00ee1000)
• #define LS1043A_FMAN_ADDR (LS1043A_IMMR + 0x00a00000)
• #define LS1043A_BMAN_ADDR (LS1043A_IMMR + 0x00890000)
• #define LS1043A_QMAN_ADDR (LS1043A_IMMR + 0x00880000)
• #define GIC_BASE_ADDR 0x01402000
• #define GIC_SIZE 0x1000

SIZE_4KB? (and so on in further locations below?)

• #define GICDIST_BASE_ADDR 0x01401000
• #define GICDIST_SIZE 0x1000
• #define DUART1_BASE_ADDR 0x21C0000
• #define DUART1_SIZE 0x1000
• #define DUART2_BASE_ADDR 0x21D0000
• #define DUART2_SIZE 0x1000
• #define WDOG1_BASE_ADDR 0x02AD0000
• #define WDOG2_BASE_ADDR 0x02AE0000
• #define WDOG3_BASE_ADDR 0x02A70000
• #define WDOG4_BASE_ADDR 0x02A80000
• #define WDOG5_BASE_ADDR 0x02A90000
• #define WDOG_SIZE 0x1000

• #define WDOG_WCR_OFFSET		0
  

• #define WDOG_WSR_OFFSET		2
  

• #define WDOG_WRSR_OFFSET	4
  

• #define WDOG_WICR_OFFSET	6
  

• #define WDOG_WCR_WT		(0xFF << 8)
  

• #define WDOG_WCR_WDE		(1 << 2)
  

• #define WDOG_SERVICE_SEQ1	0x5555
  

• #define WDOG_SERVICE_SEQ2	0xAAAA
  

• #define WDOG_WCR_WDZST 0x1
• #define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
• #define I2C0_BASE_ADDRESS 0x02180000
• #define I2C1_BASE_ADDRESS 0x02190000
• #define I2C2_BASE_ADDRESS 0x021A0000
• #define I2C3_BASE_ADDRESS 0x02183000
• #define I2C_SIZE 0x10000
• #define DSPI_MEMORY_SIZE 0x10000
• #define DDRC_MEMORY_SIZE 0x10000
• #define SDXC_MEMORY_SIZE 0x10000
• #define LS1043A_TIMER_ADDR 0x02b00000
• #define IFC_REG_BASE_ADDR 0x1530000
• #define IFC_REG_SIZE 0x0003000
• #define SCFG_BASE_ADDR 0x1570000
• #define SCFG_SIZE 0x0010000

+/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)

+#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 +#define IDR1_PAGESIZE_MASK 0x80000000

+#define LS1043A_OCRAM1_BASE_ADDR 0x10000000 +#define LS1043A_OCRAM1_SIZE 0x00010000 /* 64KB */ +#define LS1043A_OCRAM2_BASE_ADDR 0x10010000 +#define LS1043A_OCRAM2_SIZE 0x00010000 /* 64KB */ +#define LS1043A_STM_BASE_ADDR 0x12000000 +#define LS1043A_STM_SIZE 0x01000000 /* 16MB */ +#define LS1043A_DCSR_BASE_ADDR 0x20000000 +#define LS1043A_DCSR_SIZE 0x04000000 /* 64MB */ +#define LS1043A_QSPI_BASE_ADDR 0x40000000 +#define LS1043A_QSPI_SIZE 0x20000000 /* 512MB */ +#define LS1043A_IFC_REGION1_BASE_ADDR 0x60000000 +#define LS1043A_IFC_REGION1_BASE_SIZE 0x20000000 /* 512MB */ +#define LS1043A_DRAM1_BASE_ADDR 0x0080000000 +#define LS1043A_DRAM1_SIZE 0x0080000000 /* 2GB */ +#define LS1043A_QMAN_SWP_BASE_ADDR 0x0500000000 +#define LS1043A_QMAN_SWP_SIZE 0x0080000000 /* 128MB */ +#define LS1043A_BMAN_SWP_BASE_ADDR 0x0508000000 +#define LS1043A_BMAN_SWP_SIZE 0x0080000000 /* 128MB */ +#define LS1043A_IFC_REGION2_BASE_ADDR 0x0620000000 +#define LS1043A_IFC_REGION2_BASE_SIZE 0x00E0000000 /* 3.5GB */ +#define LS1043A_DRAM2_BASE_ADDR 0x0880000000 +#define LS1043A_DRAM2_SIZE 0x0780000000 /* 30GB */ +#define LS1043A_SERDES_ADDR (LS1043A_IMMR + 0xEA0000) +#define LS1043A_SRDS_1 +#define LS1043A_PCI_EXP1_BASE_ADDR 0x4000000000 +#define LS1043A_PCI_EXP1_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_PCI_EXP2_BASE_ADDR 0x4800000000 +#define LS1043A_PCI_EXP2_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_PCI_EXP3_BASE_ADDR 0x5000000000 +#define LS1043A_PCI_EXP3_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_DRAM3_BASE_ADDR 0x8800000000 +#define LS1043A_DRAM3_SIZE 0x7800000000 /* 480GB */

+/*

• • CPLD
• */

+#define LS1043A_CPLD_BASE 0x7fb00000

+/*

• • Global defines
• */

+#define NOR_BOOT 0x0 +#define NAND_BOOT 0x1 +#define SD_BOOT 0x2

+/* PCI controllers addresses */ +#define LS1043A_PCIE1_PHYS_BASE 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_BASE 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_BASE 0x5000000000ULL

+#define LS1043A_PCIE1_PHYS_ADDR 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_ADDR 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_ADDR 0x5000000000ULL

+#define LS1043A_PCIE1_ADDR 0x03600000 +#define LS1043A_PCIE2_ADDR 0x03500000 +#define LS1043A_PCIE3_ADDR 0x03600000

+/* PCIe */ +#define LS1043A_LS_PCI /* Enable PCI/PCIE */ +#define LS1043A_LS_PCIE1 /* PCIE controler 1 */ +#define LS1043A_LS_PCIE2 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE3 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */

+#define LS1043A_LS_PCI_64BIT

+#define LS1043A_LS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define LS1043A_LS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define LS1043A_LS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define LS1043A_LS_PCIE_CFG1_SIZE 0x00001000 /* 4k */

+#define LS1043A_LS_PCIE_IO_BUS 0x00000000 +#define LS1043A_LS_PCIE_IO_PHYS_OFF 0x00010000 +#define LS1043A_LS_PCIE_IO_SIZE 0x00010000 /* 64k */

+#define LS1043A_LS_PCIE_MEM_BUS 0x40000000 +#define LS1043A_LS_PCIE_MEM_PHYS_OFF 0x40000000 +#define LS1043A_LS_PCIE_MEM_SIZE 0x40000000 /* 1 GB */

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c new file mode 100644 index 0000000..7159749 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c @@ -0,0 +1,103 @@ +/** Common.c +* +* Copyright (c) 2016, Freescale Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <Library/PlatformLib.h> +#include <Library/DebugLib.h>

+UINT32 +__Div64_32 (

• IN UINT64 *N,
• IN UINT32 Base
• )

+{

• UINT64 Rem = *N;
• UINT64 b = Base;
• UINT64 Res, d = 1;
• UINT32 High = Rem >> 32;
• /** Reduce the thing a bit first */
• Res = 0;
• if (High >= Base) {
• High /= Base;
• Res = (UINT64) High << 32;
• Rem -= (UINT64) (High*Base) << 32;
• }
• while ((UINTN)b > 0 && b < Rem) {
• b = b+b;
• d = d+d;
• }
• do {
• if (Rem >= b) {

•  Rem -= b;
  

•  Res += d;
  

• }
• b >>= 1;
• d >>= 1;
• } while (d);
• *N = Res;
• return Rem;

+}

+/*

• • PrINT32 Sizes As "Xxx KiB", "Xxx.Y KiB", "Xxx MiB", "Xxx.Y MiB",
• • Xxx GiB, Xxx.Y GiB, Etc As Needed; Allow for Optional Trailing String
• • (Like "\n")
• */

+VOID +PrintSize (

• IN UINT64 Size,
• IN CONST INT8 *S
• )

+{

• UINT64 M = 0, N;
• UINT64 F;
• static CONST INT8 Names[] = {'E', 'P', 'T', 'G', 'M', 'K'};
• UINT64 D = 10 * ARRAY_SIZE(Names);
• CHAR8 C = 0;
• UINT32 I;
• for (I = 0; I < ARRAY_SIZE(Names); I++, D -= 10) {
• if (Size >> D) {

•  C = Names[I];
  

•  break;
  

• }
• }
• if (!C) {
• DEBUG((EFI_D_ERROR, "%Ld Bytes,\n %a", Size, S));
• return;
• }
• N = Size >> D;
• F = Size & ((1ULL << D) - 1);
• /* if There'S A Remainder, Deal With It */

Capitalization above makes my forehead wrinkle slightly. Could just say "Deal with any remainder.".

• if (F) {
• M = (10ULL * F + (1ULL << (D - 1))) >> D;
• if (M >= 10) {

•       M -= 10;
  

•       N += 1;
  

• }
• }
• DEBUG((EFI_D_ERROR, "%Ld", N));
• if (M) {
• DEBUG((EFI_D_ERROR, ".%Ld", M));
• }
• DEBUG((EFI_D_ERROR, " %ciB, %a ", C, S));

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c new file mode 100644 index 0000000..4fcb8a3 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c @@ -0,0 +1,107 @@ +/** LS1043aRdb.c +* +* RDB specific Library for LS1043A SoC, containing functions to initialize +* RDB boards. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Ppi/ArmMpCoreInfo.h> +#include <Library/PlatformLib.h>

+/**

• Return the current Boot Mode
• This function returns the boot reason on the platform

+**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode (

• VOID
• )

+{

• return BOOT_WITH_FULL_CONFIGURATION;

+}

+/**

• Placeholder for Platform Initialization

+**/ +RETURN_STATUS +ArmPlatformInitialize (

• IN UINTN MpId
• )

+{

• return RETURN_SUCCESS;

+}

+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {

• {
• // Cluster 0, Core 0
• 0x0, 0x0,
• // MP Core MailBox Set/Get/Clear Addresses and Clear Value
• (EFI_PHYSICAL_ADDRESS)0,
• (EFI_PHYSICAL_ADDRESS)0,
• (EFI_PHYSICAL_ADDRESS)0,
• (UINT64)0xFFFFFFFF
• },

+};

+EFI_STATUS +PrePeiCoreGetMpCoreInfo (

• OUT UINTN *CoreCount,
• OUT ARM_CORE_INFO **ArmCoreTable
• )

+{

• *CoreCount = sizeof(LS1043aMpCoreInfoCTA53x4) / sizeof(ARM_CORE_INFO);
• *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
• return EFI_SUCCESS;

+}

+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };

+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {

• {
• EFI_PEI_PPI_DESCRIPTOR_PPI,
• &mArmMpCoreInfoPpiGuid,
• &mMpCoreInfoPpi
• }

+};

+VOID +ArmPlatformGetPlatformPpiList (

• OUT UINTN *PpiListSize,
• OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
• )

+{

• *PpiListSize = sizeof(gPlatformPpiTable);
• *PpiList = gPlatformPpiTable;

+}

+UINTN +ArmPlatformGetCorePosition (

• IN UINTN MpId
• )

+{

• return 1;

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S new file mode 100644 index 0000000..5d9807f --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S @@ -0,0 +1,61 @@ +# @file +# +# Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#

+#include <AsmMacroIoLib.h> +#include <AsmMacroIoLibV8.h> +#include <AutoGen.h>

+.text +.align 2

+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)

+GCC_ASM_IMPORT(ArmReadMpidr)

+//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore):

• and x1, x0, #3
• mov x0, #0
• cbnz x1, 1f
• mov x0, #1

+1:

• ret

+ASM_PFX(ArmPlatformPeiBootAction): +EL1_OR_EL2_OR_EL3(x0) +1: +2:

• ret

+3:

• LoadConstantToReg(FixedPcdGet32(PcdCounterFrequency), x0)
• msr cntfrq_el0, x0
• ret

+//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):

• LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), x0)
• ldrh w0, [x0]
• ret

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf new file mode 100644 index 0000000..e09d940 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf @@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = LS1043aRdbLib
• FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = ArmPlatformLib

+[Packages]

• MdePkg/MdePkg.dec
• MdeModulePkg/MdeModulePkg.dec
• EmbeddedPkg/EmbeddedPkg.dec
• ArmPkg/ArmPkg.dec
• ArmPlatformPkg/ArmPlatformPkg.dec
• OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec

+[LibraryClasses]

• IoLib
• ArmLib
• MemoryAllocationLib
• I2cLib
• DdrLib
• SocLib

+[Sources.common]

• LS1043aRdbHelper.S | GCC
• LS1043aRdb.c
• LS1043aRdbMem.c
• Common.c

+[FeaturePcd]

• gEmbeddedTokenSpaceGuid.PcdCacheEnable

+[FixedPcd]

• gArmTokenSpaceGuid.PcdArmPrimaryCore
• gArmTokenSpaceGuid.PcdFdBaseAddress
• gArmTokenSpaceGuid.PcdFdSize
• gArmTokenSpaceGuid.PcdSystemMemoryBase
• gArmTokenSpaceGuid.PcdSystemMemorySize
• gArmPlatformTokenSpaceGuid.PcdCounterFrequency

As a generic OCD comment on the above - could Packages, LibraryClasses and *Pcd be alphabetically sorted within each section please?

diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c new file mode 100644 index 0000000..ef93623 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c @@ -0,0 +1,149 @@ +/** LS1043aRdbMem.c +* +* RDB memory specific Library for LS1043A SoC. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h>

+#include <Library/PlatformLib.h>

+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25

Since this value will always be known at compile time (and unlikely to change frequently), could this be a NUM_* instead of MAX_*, and the code then stick with the ASSERT that Index < at the end?

+/**

• Return the Virtual Memory Map of your platform
• This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
• @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-

•                                Virtual Memory mapping. This array must be ended by a zero-filled
  

•                                entry
  

+**/ +VOID +ArmPlatformGetVirtualMemoryMap (

• IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
• )

+{

• ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
• UINTN Index = 0;
• ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
• ASSERT(VirtualMemoryMap != NULL);
• VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));

Why cast a VOID * to they type of the pointer it is being assigned to on assignment? This could benefit from a temporary variable to shorten line length.

• if (VirtualMemoryTable == NULL) {
• return;
• }
• if (FeaturePcdGet(PcdCacheEnable) == TRUE) {

If the cache is not enabled, I don't think the platform port can be specification compliant. I.e., if there is some particular reason for this, the Pcd should possibly be named for that reason.

• CacheAttributes = DDR_ATTRIBUTES_CACHED;
• } else {
• CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
• }
• // DRAM1 (Must be 1st entry)
• VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // CCSR Space
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_CCSR_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
• // OCRAM1 Space
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_OCRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_OCRAM1_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_OCRAM1_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // OCRAM2 Space
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_OCRAM2_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_OCRAM2_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_OCRAM2_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // IFC region 1
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC_REGION1_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION1_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_IFC_REGION1_BASE_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
• // QMAN SWP
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SWP_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SWP_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_QMAN_SWP_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
• // BMAN SWP
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SWP_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SWP_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_BMAN_SWP_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
• // IFC region 2
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC_REGION2_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION2_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_IFC_REGION2_BASE_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // DRAM2
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_DRAM2_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM2_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM2_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // PCIe1
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP1_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP1_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP1_BASE_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
• // PCIe2
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP2_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP2_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP2_BASE_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
• // PCIe3
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP3_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP3_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP3_BASE_SIZE;
• VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
• // DRAM3
• VirtualMemoryTable[++Index].PhysicalBase = LS1043A_DRAM3_BASE_ADDR;
• VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM3_BASE_ADDR;
• VirtualMemoryTable[Index].Length = LS1043A_DRAM3_SIZE;
• VirtualMemoryTable[Index].Attributes = CacheAttributes;
• // End of Table
• VirtualMemoryTable[++Index].PhysicalBase = 0;
• VirtualMemoryTable[Index].VirtualBase = 0;
• VirtualMemoryTable[Index].Length = 0;
• VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;

(Dou you even need to set the Attributes at this point? If so, maybe we should just create a REGION_ATTRIBUTE_INVALID?)

• ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
• *VirtualMemoryMap = VirtualMemoryTable;

+}

1.9.1

Hi Ard,

Please see my replies inline.

From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] Sent: Tuesday, October 18, 2016 2:51 PM

On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:

...

From: Sakar Arora sakar.arora@nxp.com

NXP/FSL's LS1043A RDB board houses 2 GB DDR4 SDRAM.

There is a DDR controller IP which controls access to this SDRAM.

This patch adds a library which allows required initialization of

this

...

controller. This library executes out of the XIP NOR flash mememory.

Signed-off-by: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com

---

Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h | 190

+++++++++++++++++++++

...

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c | 188

++++++++++++++++++++

...

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf | 41 +++++ 3 files changed, 419 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c create mode 100644

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf

...

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h

Please declare this library class in the [LibraryClasses] section of the package .dec file

...

new file mode 100644 index 0000000..0d715fb --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h @@ -0,0 +1,190 @@ +/** @Ddr.h

• Header defining the Ddr controller constants (Base addresses,

+sizes, flags),

• function prototype, structures etc
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

• This program and the accompanying materials are licensed and made
• available under the terms and conditions of the BSD License which
• accompanies this distribution. The full text of the license may be
• found at http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
• BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+**/

+#ifndef __DDR_H__ +#define __DDR_H__

+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PlatformLib.h>

+/* DDR4 fixed timing */ +#define LS1043A_CS0_BNDS 0x0000007f /* 0x000 */ +#define LS1043A_CS0_CONFIG 0x80010322 /* 0x080 */ +#define LS1043A_TIMING_CFG_3 0x020C1000 /* 0x100 */ +#define LS1043A_TIMING_CFG_0 0xD0550018 /* 0x104 */ +#define LS1043A_TIMING_CFG_1 0xC2C68C42 /* 0x108 */ +#define LS1043A_TIMING_CFG_2 0x0048C114 /* 0x10c */ +#define LS1043A_DDR_SDRAM_CFG 0x450C000C /* 0x110 */ +#define LS1043A_DDR_SDRAM_CFG_2 0x00401010 /* 0x114 */ +#define LS1043A_DDR_SDRAM_MODE 0x01010214 /* 0x118 */ +#define LS1043A_DDR_SDRAM_INTERVAL 0x18600618 /* 0x124 */ +#define LS1043A_DDR_SDRAM_CLK_CNTL 0x02000000 /* 0x130 */ +#define LS1043A_TIMING_CFG_4 0x00000002 /* 0x160 */ +#define LS1043A_TIMING_CFG_5 0x04401400 /* 0x164 */ +#define LS1043A_TIMING_CFG_7 0x13300000 /* 0x16c */ +#define LS1043A_DDR_ZQ_CNTL 0x8A090705 /* 0x170 */ +#define LS1043A_DDR_WRLVL_CNTL 0x8655F606 /* 0x174 */ +#define LS1043A_DDR_WRLVL_CNTL_2 0x05070600 /* 0x190 */ +#define LS1043A_DDR_SDRAM_MODE_9 0x00000400 /* 0x220 */ +#define LS1043A_DDR_SDRAM_MODE_10 0x04000000 /* 0x224 */ +#define LS1043A_TIMING_CFG_8 0x03115600 /* 0x250 */ +#define LS1043A_DDRCDR_1 0x80040000 /* 0xb28 */ +#define LS1043A_DDRCDR_2 0x0000A181 /* 0xb2c */

+#define LS1043A_DDR_SDRAM_CFG_MEM_EN 0x80000000

+/**

• DDR memory controller registers

+**/ +struct CcsrDdr {

• UINT32 Cs0Bnds; /** Chip Select 0 Memory

Bounds */

...

• CHAR8 Res04[4];
• UINT32 Cs1Bnds; /** Chip Select 1 Memory

Bounds */

...

• CHAR8 Res0c[4];
• UINT32 Cs2Bnds; /** Chip Select 2 Memory

Bounds */

...

• CHAR8 Res14[4];
• UINT32 Cs3Bnds; /** Chip Select 3 Memory

Bounds */

...

• CHAR8 Res1c[100];
• UINT32 Cs0Config; /** Chip Select Configuration

*/

...

• UINT32 Cs1Config; /** Chip Select Configuration

*/

...

• UINT32 Cs2Config; /** Chip Select Configuration

*/

...

• UINT32 Cs3Config; /** Chip Select Configuration

*/

...

• CHAR8 Res90[48];
• UINT32 Cs0Config2; /** Chip Select Configuration

2 */

...

• UINT32 Cs1Config2; /** Chip Select Configuration

2 */

...

• UINT32 Cs2Config2; /** Chip Select Configuration

2 */

...

• UINT32 Cs3Config2; /** Chip Select Configuration

2 */

...

• CHAR8 Resd0[48];
• UINT32 TimingCfg3; /** SDRAM Timing

Configuration 3 */

...

• UINT32 TimingCfg0; /** SDRAM Timing

Configuration 0 */

...

• UINT32 TimingCfg1; /** SDRAM Timing

Configuration 1 */

...

• UINT32 TimingCfg2; /** SDRAM Timing

Configuration 2 */

...

• UINT32 SdramCfg; /** SDRAM Control

Configuration */

...

• UINT32 SdramCfg2; /** SDRAM Control

Configuration 2 */

...

• UINT32 SdramMode; /** SDRAM Mode Configuration

*/

...

• UINT32 SdramMode2; /** SDRAM Mode Configuration

2 */

...

• UINT32 SdramMdCntl; /** SDRAM Mode Control */
• UINT32 SdramInterval; /** SDRAM Interval Configuration */
• UINT32 SdramDataInit; /** SDRAM Data initialization */
• CHAR8 Res12c[4];
• UINT32 SdramClkCntl; /** SDRAM Clock Control */
• CHAR8 Res134[20];
• UINT32 InitAddr; /** training init addr */
• UINT32 InitExtAddr; /** training init extended

addr */

...

• CHAR8 Res150[16];
• UINT32 TimingCfg4; /** SDRAM Timing

Configuration 4 */

...

• UINT32 TimingCfg5; /** SDRAM Timing

Configuration 5 */

...

• UINT32 TimingCfg6; /** SDRAM Timing

Configuration 6 */

...

• UINT32 TimingCfg7; /** SDRAM Timing

Configuration 7 */

...

• UINT32 DdrZqCntl; /** ZQ calibration control*/
• UINT32 DdrWrlvlCntl; /** write leveling control*/
• CHAR8 Reg178[4];
• UINT32 DdrSrCntr; /** self refresh counter */
• UINT32 DdrSdramRcw1; /** Control Words 1 */
• UINT32 DdrSdramRcw2; /** Control Words 2 */
• CHAR8 Reg188[8];
• UINT32 DdrWrlvlCntl2; /** write leveling control 2 */
• UINT32 DdrWrlvlCntl3; /** write leveling control 3 */
• CHAR8 Res198[8];
• UINT32 DdrSdramRcw3;
• UINT32 DdrSdramRcw4;
• UINT32 DdrSdramRcw5;
• UINT32 DdrSdramRcw6;
• CHAR8 Res1b0[80];
• UINT32 SdramMode3; /** SDRAM Mode Configuration

3 */

...

• UINT32 SdramMode4; /** SDRAM Mode Configuration

4 */

...

• UINT32 SdramMode5; /** SDRAM Mode Configuration

5 */

...

• UINT32 SdramMode6; /** SDRAM Mode Configuration

6 */

...

• UINT32 SdramMode7; /** SDRAM Mode Configuration

7 */

...

• UINT32 SdramMode8; /** SDRAM Mode Configuration

8 */

...

• CHAR8 Res218[8];
• UINT32 SdramMode9; /** SDRAM Mode Configuration

9 */

...

• UINT32 SdramMode10; /** SDRAM Mode Configuration

10 */

...

• UINT32 SdramMode11; /** SDRAM Mode Configuration

11 */

...

• UINT32 SdramMode12; /** SDRAM Mode Configuration

12 */

...

• UINT32 SdramMode13; /** SDRAM Mode Configuration

13 */

...

• UINT32 SdramMode14; /** SDRAM Mode Configuration

14 */

...

• UINT32 SdramMode15; /** SDRAM Mode Configuration

15 */

...

• UINT32 SdramMode16; /** SDRAM Mode Configuration

16 */

...

• CHAR8 Res240[16];
• UINT32 TimingCfg8; /* SDRAM Timing Configuration 8 */
• CHAR8 Res254[12];
• UINT32 SdramCfg3;
• CHAR8 Res264[412];
• UINT32 DqMap0;
• UINT32 DqMap1;
• UINT32 DqMap2;
• UINT32 DqMap3;
• CHAR8 Res410[1808];
• UINT32 DdrDsr1; /** Debug Status 1 */
• UINT32 DdrDsr2; /** Debug Status 2 */
• UINT32 DdrCdr1; /** Control Driver 1 */
• UINT32 DdrCdr2; /** Control Driver 2 */
• CHAR8 ResB30[200];
• UINT32 IpRev1; /** IP Block Revision 1 */
• UINT32 IpRev2; /** IP Block Revision 2 */
• UINT32 Eor; /** Enhanced Optimization

Register */

...

• CHAR8 ResC04[252];
• UINT32 Mtcr; /** Memory Test Control

Register */

...

• CHAR8 ResD04[28];
• UINT32 Mtp1; /** Memory Test Pattern 1 */
• UINT32 Mtp2; /** Memory Test Pattern 2 */
• UINT32 Mtp3; /** Memory Test Pattern 3 */
• UINT32 Mtp4; /** Memory Test Pattern 4 */
• UINT32 Mtp5; /** Memory Test Pattern 5 */
• UINT32 Mtp6; /** Memory Test Pattern 6 */
• UINT32 Mtp7; /** Memory Test Pattern 7 */
• UINT32 Mtp8; /** Memory Test Pattern 8 */
• UINT32 Mtp9; /** Memory Test Pattern 9 */
• UINT32 Mtp10; /** Memory Test Pattern 10 */
• CHAR8 ResD48[184];
• UINT32 DataErrInjectHi; /** Data Path Err Injection

Mask High */

...

• UINT32 DataErrInjectLo; /** Data Path Err Injection

Mask Low */

...

• UINT32 EccErrInject; /** Data Path Err Injection

Mask ECC */

...

• CHAR8 ResE0c[20];
• UINT32 CaptureDataHi; /** Data Path Read Capture High */
• UINT32 CaptureDataLo; /** Data Path Read Capture Low */
• UINT32 CaptureEcc; /** Data Path Read Capture

ECC */

...

• CHAR8 ResE2c[20];
• UINT32 ErrDetect; /** Error Detect */
• UINT32 ErrDisable; /** Error Disable */
• UINT32 ErrIntEn;
• UINT32 CaptureAttributes; /** Error Attrs Capture */
• UINT32 CaptureAddress; /** Error Addr Capture */
• UINT32 CaptureExtAddress; /** Error Extended Addr

Capture */

...

• UINT32 ErrSbe; /** Single-Bit ECC Error Management

*/

...

• CHAR8 ResE5c[164];
• UINT32 Debug[32]; /** Debug_1 to Debug_32 */
• CHAR8 ResF80[128];

+};

+/**

• Main function to initialize DDR
• **/

+VOID +DramInit(

• );

+/**

• Function to dump DDRC registers

+**/ +VOID +DdrRegDump (

• VOID
• );

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c new file mode 100644 index 0000000..1c33de4 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c @@ -0,0 +1,188 @@ +/** @DdrLib.c

• Ddr Library containing functions to initialize ddr controller
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

• This program and the accompanying materials are licensed and made
• available under the terms and conditions of the BSD License which
• accompanies this distribution. The full text of the license may be
• found at http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
• BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+**/

+#include <Library/Ddr.h> +#include <Library/BaseLib.h>

+#define Uswap32(X) \

•   ((((X) & 0xff000000) >> 24) | \
  

•    (((X) & 0x00ff0000) >>  8) | \
  

•    (((X) & 0x0000ff00) <<  8) | \
  

•    (((X) & 0x000000ff) << 24))
  

+#define DDRMC_DELAY 10000

+/**

• Function to dump DDRC registers

+**/

+VOID +DdrRegDump (

• VOID
• )

+{

• struct CcsrDdr *Ddr = (VOID *)LS1043A_DDR_ADDR;
• DEBUG((EFI_D_INFO, "Cs0Bnds =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Bnds)));

• DEBUG((EFI_D_INFO, "Cs1Bnds =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Bnds)));

• DEBUG((EFI_D_INFO, "Cs2Bnds =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Bnds)));

• DEBUG((EFI_D_INFO, "Cs3Bnds =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Bnds)));

• DEBUG((EFI_D_INFO, "Cs0Config =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config)));

• DEBUG((EFI_D_INFO, "Cs1Config =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config)));

• DEBUG((EFI_D_INFO, "Cs2Config =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config)));

• DEBUG((EFI_D_INFO, "Cs3Config =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config)));

• DEBUG((EFI_D_INFO, "Cs0Config2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config2)));

• DEBUG((EFI_D_INFO, "Cs1Config2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config2)));

• DEBUG((EFI_D_INFO, "Cs2Config2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config2)));

• DEBUG((EFI_D_INFO, "Cs3Config2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config2)));

• DEBUG((EFI_D_INFO, "TimingCfg3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg3)));

• DEBUG((EFI_D_INFO, "TimingCfg0 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg0)));

• DEBUG((EFI_D_INFO, "TimingCfg1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg1)));

• DEBUG((EFI_D_INFO, "TimingCfg2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg2)));

• DEBUG((EFI_D_INFO, "SdramCfg =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg)));

• DEBUG((EFI_D_INFO, "SdramCfg2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg2)));

• DEBUG((EFI_D_INFO, "SdramMode =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode)));

• DEBUG((EFI_D_INFO, "SdramMode2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode2)));

• DEBUG((EFI_D_INFO, "SdramMdCntl =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMdCntl)));

• DEBUG((EFI_D_INFO, "SdramInterval =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramInterval)));

• DEBUG((EFI_D_INFO, "SdramDataInit =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramDataInit)));

• DEBUG((EFI_D_INFO, "SdramClkCntl =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramClkCntl)));

• DEBUG((EFI_D_INFO, "InitAddr =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->InitAddr)));

• DEBUG((EFI_D_INFO, "InitExtAddr =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->InitExtAddr)));

• DEBUG((EFI_D_INFO, "TimingCfg4 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg4)));

• DEBUG((EFI_D_INFO, "TimingCfg5 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg5)));

• DEBUG((EFI_D_INFO, "TimingCfg6 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg6)));

• DEBUG((EFI_D_INFO, "TimingCfg7 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg7)));

• DEBUG((EFI_D_INFO, "DdrZqCntl =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrZqCntl)));

• DEBUG((EFI_D_INFO, "DdrWrlvlCntl =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl)));

• DEBUG((EFI_D_INFO, "DdrSrCntr =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSrCntr)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw1)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw2)));

• DEBUG((EFI_D_INFO, "DdrWrlvlCntl2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl2)));

• DEBUG((EFI_D_INFO, "DdrWrlvlCntl3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl3)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw3)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw4 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw4)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw5 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw5)));

• DEBUG((EFI_D_INFO, "DdrSdramRcw6 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw6)));

• DEBUG((EFI_D_INFO, "SdramMode3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode3)));

• DEBUG((EFI_D_INFO, "SdramMode4 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode4)));

• DEBUG((EFI_D_INFO, "SdramMode5 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode5)));

• DEBUG((EFI_D_INFO, "SdramMode6 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode6)));

• DEBUG((EFI_D_INFO, "SdramMode7 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode7)));

• DEBUG((EFI_D_INFO, "SdramMode8 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode8)));

• DEBUG((EFI_D_INFO, "SdramMode9 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode9)));

• DEBUG((EFI_D_INFO, "SdramMode10 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode10)));

• DEBUG((EFI_D_INFO, "SdramMode11 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode11)));

• DEBUG((EFI_D_INFO, "SdramMode12 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode12)));

• DEBUG((EFI_D_INFO, "SdramMode13 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode13)));

• DEBUG((EFI_D_INFO, "SdramMode14 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode14)));

• DEBUG((EFI_D_INFO, "SdramMode15 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode15)));

• DEBUG((EFI_D_INFO, "SdramMode16 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode16)));

• DEBUG((EFI_D_INFO, "TimingCfg8 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg8)));

• DEBUG((EFI_D_INFO, "SdramCfg3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg3)));

• DEBUG((EFI_D_INFO, "DqMap0 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap0)));

• DEBUG((EFI_D_INFO, "DqMap1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap1)));

• DEBUG((EFI_D_INFO, "DqMap2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap2)));

• DEBUG((EFI_D_INFO, "DqMap3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap3)));

• DEBUG((EFI_D_INFO, "DdrDsr1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr1)));

• DEBUG((EFI_D_INFO, "DdrDsr2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr2)));

• DEBUG((EFI_D_INFO, "DdrCdr1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr1)));

• DEBUG((EFI_D_INFO, "DdrCdr2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr2)));

• DEBUG((EFI_D_INFO, "IpRev1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev1)));

• DEBUG((EFI_D_INFO, "IpRev2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev2)));

• DEBUG((EFI_D_INFO, "Eor = 0x%x\n",MmioReadBe32((UINTN)&Ddr-

Eor)));

• DEBUG((EFI_D_INFO, "Mtcr =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtcr)));

• DEBUG((EFI_D_INFO, "Mtp1 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp1)));

• DEBUG((EFI_D_INFO, "Mtp2 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp2)));

• DEBUG((EFI_D_INFO, "Mtp3 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp3)));

• DEBUG((EFI_D_INFO, "Mtp4 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp4)));

• DEBUG((EFI_D_INFO, "Mtp5 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp5)));

• DEBUG((EFI_D_INFO, "Mtp6 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp6)));

• DEBUG((EFI_D_INFO, "Mtp7 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp7)));

• DEBUG((EFI_D_INFO, "Mtp8 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp8)));

• DEBUG((EFI_D_INFO, "Mtp9 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp9)));

• DEBUG((EFI_D_INFO, "Mtp10 =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp10)));

• DEBUG((EFI_D_INFO, "DataErrInjectHi =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectHi)));

• DEBUG((EFI_D_INFO, "DataErrInjectLo =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectLo)));

• DEBUG((EFI_D_INFO, "EccErrInject =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->EccErrInject)));

• DEBUG((EFI_D_INFO, "CaptureDataHi =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataHi)));

• DEBUG((EFI_D_INFO, "CaptureDataLo =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataLo)));

• DEBUG((EFI_D_INFO, "CaptureEcc =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureEcc)));

• DEBUG((EFI_D_INFO, "ErrDetect =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDetect)));

• DEBUG((EFI_D_INFO, "ErrDisable =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDisable)));

• DEBUG((EFI_D_INFO, "ErrIntEn =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrIntEn)));

• DEBUG((EFI_D_INFO, "CaptureAttributes =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAttributes)));

• DEBUG((EFI_D_INFO, "CaptureAddress =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAddress)));

• DEBUG((EFI_D_INFO, "CaptureExtAddress =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureExtAddress)));

• DEBUG((EFI_D_INFO, "ErrSbe =

+0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrSbe)));

• DEBUG((EFI_D_ERROR,"\n"));

+}

+/**

• Function to initialize DDR
• **/

+VOID +DramInit (

• )

+{

• struct CcsrDdr *Ddr;

•   UINT32 Count, Delay = DDRMC_DELAY;
  

• Ddr = (VOID *)LS1043A_DDR_ADDR;
• MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG);

Where is MmioWriteBe32() defined?

I sent a separate patch for ARM IoLib on EDK2 mailing list where we added the support for MmioWriteBe32: https://lists.01.org/pipermail/edk2-devel/2016-October/002791.html

Now that the discussion seems concluded, I will change the patch accordingly.

...

• MmioWriteBe32((UINTN)&Ddr->Cs0Bnds, LS1043A_CS0_BNDS);
• MmioWriteBe32((UINTN)&Ddr->Cs0Config, LS1043A_CS0_CONFIG);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg0, LS1043A_TIMING_CFG_0);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg1, LS1043A_TIMING_CFG_1);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg2, LS1043A_TIMING_CFG_2);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg3, LS1043A_TIMING_CFG_3);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg4, LS1043A_TIMING_CFG_4);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg5, LS1043A_TIMING_CFG_5);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg7, LS1043A_TIMING_CFG_7);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg8, LS1043A_TIMING_CFG_8);
• MmioWriteBe32((UINTN)&Ddr->SdramCfg2, LS1043A_DDR_SDRAM_CFG_2);
• MmioWriteBe32((UINTN)&Ddr->SdramMode, LS1043A_DDR_SDRAM_MODE);
• MmioWriteBe32((UINTN)&Ddr->SdramMode2, 0);
• MmioWriteBe32((UINTN)&Ddr->SdramInterval,
• LS1043A_DDR_SDRAM_INTERVAL);
• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl, LS1043A_DDR_WRLVL_CNTL);
• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl2,

LS1043A_DDR_WRLVL_CNTL_2);

...

• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl3, 0);
• MmioWriteBe32((UINTN)&Ddr->DdrCdr1, LS1043A_DDRCDR_1);
• MmioWriteBe32((UINTN)&Ddr->DdrCdr2, LS1043A_DDRCDR_2);
• MmioWriteBe32((UINTN)&Ddr->SdramClkCntl,
• LS1043A_DDR_SDRAM_CLK_CNTL);
• MmioWriteBe32((UINTN)&Ddr->DdrZqCntl, LS1043A_DDR_ZQ_CNTL);
• MmioWriteBe32((UINTN)&Ddr->SdramMode9, LS1043A_DDR_SDRAM_MODE_9);
• MmioWriteBe32((UINTN)&Ddr->SdramMode10, LS1043A_DDR_SDRAM_MODE_10);
• MmioWriteBe32((UINTN)&Ddr->Cs0Config2, 0);
• for(Count = 0; Count < Delay; Count++)

•           ;
  

• MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG

•                 | LS1043A_DDR_SDRAM_CFG_MEM_EN);
  

• return;

No 'return's add the end of void functions please

Ok.

...

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf new file mode 100644 index 0000000..e8e3aed --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf @@ -0,0 +1,41 @@ +#/** DdrLib.inf +# +# Component description file for DdrLib module # # Copyright (c) +2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials # are licensed and +made available under the terms and conditions of the BSD License # +which accompanies this distribution. The full text of the license +may be found at # http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+# +#**/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = DdrLib
• FILE_GUID = 8ecefc8f-a2c4-4091-b31f-

20f7aeb0567f

Please use a fresh GUID

Ok.

...

• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = DdrLib

+[Sources.common]

• DdrLib.c

+[LibraryClasses]

• ArmLib
• IoLib
• BaseMemoryLib
• BaseLib
• SocLib

+[Packages]

• EmbeddedPkg/EmbeddedPkg.dec
• MdePkg/MdePkg.dec
• MdeModulePkg/MdeModulePkg.dec
• ArmPlatformPkg/ArmPlatformPkg.dec
• OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec
• OpenPlatformPkg/Chips/Nxp/QoriqLs/NxpQoriqLs.dec

-- 1.9.1

Regards, Bhupesh

Hi Leif,

Thanks for your review.

From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: Monday, October 24, 2016 8:01 PM

On Tue, Oct 18, 2016 at 01:34:01AM +0530, Bhupesh Sharma wrote:

...

From: Sakar Arora sakar.arora@nxp.com

NXP/FSL's LS1043A RDB board houses 2 GB DDR4 SDRAM.

There is a DDR controller IP which controls access to this SDRAM.

This patch adds a library which allows required initialization of

this

...

controller. This library executes out of the XIP NOR flash mememory.

Signed-off-by: Meenakshi Aggarwal meenakshi.aggarwal@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com

---

Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h | 190

+++++++++++++++++++++

...

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c | 188

++++++++++++++++++++

...

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf | 41 +++++ 3 files changed, 419 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c create mode 100644

Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf

...

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h new file mode 100644 index 0000000..0d715fb --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Ddr.h @@ -0,0 +1,190 @@ +/** @Ddr.h

• Header defining the Ddr controller constants (Base addresses,

+sizes, flags),

• function prototype, structures etc
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

• This program and the accompanying materials are licensed and made
• available under the terms and conditions of the BSD License which
• accompanies this distribution. The full text of the license may be
• found at http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
• BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+**/

+#ifndef __DDR_H__ +#define __DDR_H__

+#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PlatformLib.h>

+/* DDR4 fixed timing */

OK, so I can see by the numbers in the comments column that there is some logical order by which the below is sorted ... but could we have a comment of what?

Sure, will add that in V2.

...

+#define LS1043A_CS0_BNDS 0x0000007f /* 0x000 */ +#define LS1043A_CS0_CONFIG 0x80010322 /* 0x080 */ +#define LS1043A_TIMING_CFG_3 0x020C1000 /* 0x100 */ +#define LS1043A_TIMING_CFG_0 0xD0550018 /* 0x104 */ +#define LS1043A_TIMING_CFG_1 0xC2C68C42 /* 0x108 */ +#define LS1043A_TIMING_CFG_2 0x0048C114 /* 0x10c */ +#define LS1043A_DDR_SDRAM_CFG 0x450C000C /* 0x110 */ +#define LS1043A_DDR_SDRAM_CFG_2 0x00401010 /* 0x114 */ +#define LS1043A_DDR_SDRAM_MODE 0x01010214 /* 0x118 */ +#define LS1043A_DDR_SDRAM_INTERVAL 0x18600618 /* 0x124 */ +#define LS1043A_DDR_SDRAM_CLK_CNTL 0x02000000 /* 0x130 */ +#define LS1043A_TIMING_CFG_4 0x00000002 /* 0x160 */ +#define LS1043A_TIMING_CFG_5 0x04401400 /* 0x164 */ +#define LS1043A_TIMING_CFG_7 0x13300000 /* 0x16c */ +#define LS1043A_DDR_ZQ_CNTL 0x8A090705 /* 0x170 */ +#define LS1043A_DDR_WRLVL_CNTL 0x8655F606 /* 0x174 */ +#define LS1043A_DDR_WRLVL_CNTL_2 0x05070600 /* 0x190 */ +#define LS1043A_DDR_SDRAM_MODE_9 0x00000400 /* 0x220 */ +#define LS1043A_DDR_SDRAM_MODE_10 0x04000000 /* 0x224 */ +#define LS1043A_TIMING_CFG_8 0x03115600 /* 0x250 */ +#define LS1043A_DDRCDR_1 0x80040000 /* 0xb28 */ +#define LS1043A_DDRCDR_2 0x0000A181 /* 0xb2c */

+#define LS1043A_DDR_SDRAM_CFG_MEM_EN 0x80000000

+/**

• DDR memory controller registers

+**/ +struct CcsrDdr {

• UINT32 Cs0Bnds; /** Chip Select 0 Memory Bounds */
• CHAR8 Res04[4];

Should not all of these by UCHAR8?

Ok, will change that in V2.

...

• UINT32 Cs1Bnds; /** Chip Select 1 Memory Bounds */
• CHAR8 Res0c[4];
• UINT32 Cs2Bnds; /** Chip Select 2 Memory Bounds */
• CHAR8 Res14[4];
• UINT32 Cs3Bnds; /** Chip Select 3 Memory Bounds */
• CHAR8 Res1c[100];
• UINT32 Cs0Config; /** Chip Select Configuration */
• UINT32 Cs1Config; /** Chip Select Configuration */
• UINT32 Cs2Config; /** Chip Select Configuration */
• UINT32 Cs3Config; /** Chip Select Configuration */
• CHAR8 Res90[48];
• UINT32 Cs0Config2; /** Chip Select Configuration 2 */
• UINT32 Cs1Config2; /** Chip Select Configuration 2 */
• UINT32 Cs2Config2; /** Chip Select Configuration 2 */
• UINT32 Cs3Config2; /** Chip Select Configuration 2 */
• CHAR8 Resd0[48];
• UINT32 TimingCfg3; /** SDRAM Timing Configuration 3 */
• UINT32 TimingCfg0; /** SDRAM Timing Configuration 0 */
• UINT32 TimingCfg1; /** SDRAM Timing Configuration 1 */
• UINT32 TimingCfg2; /** SDRAM Timing Configuration 2 */
• UINT32 SdramCfg; /** SDRAM Control Configuration */
• UINT32 SdramCfg2; /** SDRAM Control Configuration 2 */
• UINT32 SdramMode; /** SDRAM Mode Configuration */
• UINT32 SdramMode2; /** SDRAM Mode Configuration 2 */
• UINT32 SdramMdCntl; /** SDRAM Mode Control */
• UINT32 SdramInterval; /** SDRAM Interval Configuration */
• UINT32 SdramDataInit; /** SDRAM Data initialization */
• CHAR8 Res12c[4];
• UINT32 SdramClkCntl; /** SDRAM Clock Control */
• CHAR8 Res134[20];
• UINT32 InitAddr; /** training init addr */
• UINT32 InitExtAddr; /** training init extended addr */
• CHAR8 Res150[16];
• UINT32 TimingCfg4; /** SDRAM Timing Configuration 4 */
• UINT32 TimingCfg5; /** SDRAM Timing Configuration 5 */
• UINT32 TimingCfg6; /** SDRAM Timing Configuration 6 */
• UINT32 TimingCfg7; /** SDRAM Timing Configuration 7 */
• UINT32 DdrZqCntl; /** ZQ calibration control*/
• UINT32 DdrWrlvlCntl; /** write leveling control*/
• CHAR8 Reg178[4];
• UINT32 DdrSrCntr; /** self refresh counter */
• UINT32 DdrSdramRcw1; /** Control Words 1 */
• UINT32 DdrSdramRcw2; /** Control Words 2 */
• CHAR8 Reg188[8];
• UINT32 DdrWrlvlCntl2; /** write leveling control 2 */
• UINT32 DdrWrlvlCntl3; /** write leveling control 3 */
• CHAR8 Res198[8];
• UINT32 DdrSdramRcw3;
• UINT32 DdrSdramRcw4;
• UINT32 DdrSdramRcw5;
• UINT32 DdrSdramRcw6;
• CHAR8 Res1b0[80];
• UINT32 SdramMode3; /** SDRAM Mode Configuration 3 */
• UINT32 SdramMode4; /** SDRAM Mode Configuration 4 */
• UINT32 SdramMode5; /** SDRAM Mode Configuration 5 */
• UINT32 SdramMode6; /** SDRAM Mode Configuration 6 */
• UINT32 SdramMode7; /** SDRAM Mode Configuration 7 */
• UINT32 SdramMode8; /** SDRAM Mode Configuration 8 */
• CHAR8 Res218[8];
• UINT32 SdramMode9; /** SDRAM Mode Configuration 9 */
• UINT32 SdramMode10; /** SDRAM Mode Configuration 10 */
• UINT32 SdramMode11; /** SDRAM Mode Configuration 11 */
• UINT32 SdramMode12; /** SDRAM Mode Configuration 12 */
• UINT32 SdramMode13; /** SDRAM Mode Configuration 13 */
• UINT32 SdramMode14; /** SDRAM Mode Configuration 14 */
• UINT32 SdramMode15; /** SDRAM Mode Configuration 15 */
• UINT32 SdramMode16; /** SDRAM Mode Configuration 16 */
• CHAR8 Res240[16];
• UINT32 TimingCfg8; /* SDRAM Timing Configuration 8 */
• CHAR8 Res254[12];
• UINT32 SdramCfg3;
• CHAR8 Res264[412];
• UINT32 DqMap0;
• UINT32 DqMap1;
• UINT32 DqMap2;
• UINT32 DqMap3;
• CHAR8 Res410[1808];
• UINT32 DdrDsr1; /** Debug Status 1 */
• UINT32 DdrDsr2; /** Debug Status 2 */
• UINT32 DdrCdr1; /** Control Driver 1 */
• UINT32 DdrCdr2; /** Control Driver 2 */
• CHAR8 ResB30[200];
• UINT32 IpRev1; /** IP Block Revision 1 */
• UINT32 IpRev2; /** IP Block Revision 2 */
• UINT32 Eor; /** Enhanced Optimization Register */
• CHAR8 ResC04[252];
• UINT32 Mtcr; /** Memory Test Control Register */
• CHAR8 ResD04[28];
• UINT32 Mtp1; /** Memory Test Pattern 1 */
• UINT32 Mtp2; /** Memory Test Pattern 2 */
• UINT32 Mtp3; /** Memory Test Pattern 3 */
• UINT32 Mtp4; /** Memory Test Pattern 4 */
• UINT32 Mtp5; /** Memory Test Pattern 5 */
• UINT32 Mtp6; /** Memory Test Pattern 6 */
• UINT32 Mtp7; /** Memory Test Pattern 7 */
• UINT32 Mtp8; /** Memory Test Pattern 8 */
• UINT32 Mtp9; /** Memory Test Pattern 9 */
• UINT32 Mtp10; /** Memory Test Pattern 10 */
• CHAR8 ResD48[184];
• UINT32 DataErrInjectHi; /** Data Path Err Injection Mask High */
• UINT32 DataErrInjectLo; /** Data Path Err Injection Mask Low */
• UINT32 EccErrInject; /** Data Path Err Injection Mask

ECC */

...

• CHAR8 ResE0c[20];
• UINT32 CaptureDataHi; /** Data Path Read Capture High */
• UINT32 CaptureDataLo; /** Data Path Read Capture Low */
• UINT32 CaptureEcc; /** Data Path Read Capture ECC */
• CHAR8 ResE2c[20];
• UINT32 ErrDetect; /** Error Detect */
• UINT32 ErrDisable; /** Error Disable */
• UINT32 ErrIntEn;
• UINT32 CaptureAttributes; /** Error Attrs Capture */
• UINT32 CaptureAddress; /** Error Addr Capture */
• UINT32 CaptureExtAddress; /** Error Extended Addr Capture */
• UINT32 ErrSbe; /** Single-Bit ECC Error Management */
• CHAR8 ResE5c[164];
• UINT32 Debug[32]; /** Debug_1 to Debug_32 */
• CHAR8 ResF80[128];

+};

+/**

• Main function to initialize DDR
• **/

+VOID +DramInit(

• );

+/**

• Function to dump DDRC registers

+**/ +VOID +DdrRegDump (

• VOID
• );

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c new file mode 100644 index 0000000..1c33de4 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.c @@ -0,0 +1,188 @@ +/** @DdrLib.c

• Ddr Library containing functions to initialize ddr controller
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights

reserved.

...

• This program and the accompanying materials are licensed and made
• available under the terms and conditions of the BSD License which
• accompanies this distribution. The full text of the license may be
• found at http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
• BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+**/

+#include <Library/Ddr.h> +#include <Library/BaseLib.h>

+#define Uswap32(X) \

Use SwapBytes32 instead?

Ok.

...

•   ((((X) & 0xff000000) >> 24) | \
  

•    (((X) & 0x00ff0000) >>  8) | \
  

•    (((X) & 0x0000ff00) <<  8) | \
  

•    (((X) & 0x000000ff) << 24))
  

+#define DDRMC_DELAY 10000

10000 what?

Ok, will add appropriate comment here.

...

+/**

• Function to dump DDRC registers

+**/

+VOID +DdrRegDump (

• VOID
• )

+{

• struct CcsrDdr *Ddr = (VOID *)LS1043A_DDR_ADDR;
• DEBUG((EFI_D_INFO, "Cs0Bnds =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Bnds)));

These all need a space after comma. Hmm, I get a bit nervous about those MmioReadBe32 though... Because struct CcsrDdr is defined as a little-endian structure. Too feel more comfortable, I would like to have a comment at the structure definition explaining why this is, and for what reasons this is not problematic.

Sure, will add that in V2.

...

• DEBUG((EFI_D_INFO, "Cs1Bnds =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Bnds)));

Also ... this would be a lot cleaner as a macro: #define DUMP_DDR_REG(X, Y) \ DEBUG((EFI_D_INFO, "%s = 0x%x\n", #Y, MmioReadBe32((UINTN)&X->Y))) And called as: DUMP_DDR_REG(Ddr, Cs1Bnds);

Although I think it would be worth looking into checking current debug level before calling this function rather than for every register to be dumped.

Fair enough.

...

• DEBUG((EFI_D_INFO, "Cs2Bnds =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Bnds)));
• DEBUG((EFI_D_INFO, "Cs3Bnds =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Bnds)));
• DEBUG((EFI_D_INFO, "Cs0Config =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config)));
• DEBUG((EFI_D_INFO, "Cs1Config =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config)));
• DEBUG((EFI_D_INFO, "Cs2Config =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config)));
• DEBUG((EFI_D_INFO, "Cs3Config =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config)));
• DEBUG((EFI_D_INFO, "Cs0Config2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs0Config2)));
• DEBUG((EFI_D_INFO, "Cs1Config2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs1Config2)));
• DEBUG((EFI_D_INFO, "Cs2Config2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs2Config2)));
• DEBUG((EFI_D_INFO, "Cs3Config2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Cs3Config2)));
• DEBUG((EFI_D_INFO, "TimingCfg3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg3)));
• DEBUG((EFI_D_INFO, "TimingCfg0 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg0)));
• DEBUG((EFI_D_INFO, "TimingCfg1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg1)));
• DEBUG((EFI_D_INFO, "TimingCfg2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg2)));
• DEBUG((EFI_D_INFO, "SdramCfg =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg)));
• DEBUG((EFI_D_INFO, "SdramCfg2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg2)));
• DEBUG((EFI_D_INFO, "SdramMode =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode)));
• DEBUG((EFI_D_INFO, "SdramMode2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode2)));
• DEBUG((EFI_D_INFO, "SdramMdCntl =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMdCntl)));
• DEBUG((EFI_D_INFO, "SdramInterval =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramInterval)));
• DEBUG((EFI_D_INFO, "SdramDataInit =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramDataInit)));
• DEBUG((EFI_D_INFO, "SdramClkCntl =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramClkCntl)));
• DEBUG((EFI_D_INFO, "InitAddr =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->InitAddr)));
• DEBUG((EFI_D_INFO, "InitExtAddr =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->InitExtAddr)));
• DEBUG((EFI_D_INFO, "TimingCfg4 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg4)));
• DEBUG((EFI_D_INFO, "TimingCfg5 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg5)));
• DEBUG((EFI_D_INFO, "TimingCfg6 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg6)));
• DEBUG((EFI_D_INFO, "TimingCfg7 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg7)));
• DEBUG((EFI_D_INFO, "DdrZqCntl =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrZqCntl)));
• DEBUG((EFI_D_INFO, "DdrWrlvlCntl =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl)));
• DEBUG((EFI_D_INFO, "DdrSrCntr =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSrCntr)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw1)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw2)));
• DEBUG((EFI_D_INFO, "DdrWrlvlCntl2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl2)));
• DEBUG((EFI_D_INFO, "DdrWrlvlCntl3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrWrlvlCntl3)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw3)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw4 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw4)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw5 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw5)));
• DEBUG((EFI_D_INFO, "DdrSdramRcw6 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrSdramRcw6)));
• DEBUG((EFI_D_INFO, "SdramMode3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode3)));
• DEBUG((EFI_D_INFO, "SdramMode4 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode4)));
• DEBUG((EFI_D_INFO, "SdramMode5 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode5)));
• DEBUG((EFI_D_INFO, "SdramMode6 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode6)));
• DEBUG((EFI_D_INFO, "SdramMode7 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode7)));
• DEBUG((EFI_D_INFO, "SdramMode8 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode8)));
• DEBUG((EFI_D_INFO, "SdramMode9 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode9)));
• DEBUG((EFI_D_INFO, "SdramMode10 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode10)));
• DEBUG((EFI_D_INFO, "SdramMode11 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode11)));
• DEBUG((EFI_D_INFO, "SdramMode12 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode12)));
• DEBUG((EFI_D_INFO, "SdramMode13 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode13)));
• DEBUG((EFI_D_INFO, "SdramMode14 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode14)));
• DEBUG((EFI_D_INFO, "SdramMode15 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode15)));
• DEBUG((EFI_D_INFO, "SdramMode16 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramMode16)));
• DEBUG((EFI_D_INFO, "TimingCfg8 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->TimingCfg8)));
• DEBUG((EFI_D_INFO, "SdramCfg3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->SdramCfg3)));
• DEBUG((EFI_D_INFO, "DqMap0 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap0)));
• DEBUG((EFI_D_INFO, "DqMap1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap1)));
• DEBUG((EFI_D_INFO, "DqMap2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap2)));
• DEBUG((EFI_D_INFO, "DqMap3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DqMap3)));
• DEBUG((EFI_D_INFO, "DdrDsr1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr1)));
• DEBUG((EFI_D_INFO, "DdrDsr2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrDsr2)));
• DEBUG((EFI_D_INFO, "DdrCdr1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr1)));
• DEBUG((EFI_D_INFO, "DdrCdr2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DdrCdr2)));
• DEBUG((EFI_D_INFO, "IpRev1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev1)));
• DEBUG((EFI_D_INFO, "IpRev2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->IpRev2)));
• DEBUG((EFI_D_INFO, "Eor = 0x%x\n",MmioReadBe32((UINTN)&Ddr-

Eor)));

• DEBUG((EFI_D_INFO, "Mtcr =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtcr)));
• DEBUG((EFI_D_INFO, "Mtp1 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp1)));
• DEBUG((EFI_D_INFO, "Mtp2 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp2)));
• DEBUG((EFI_D_INFO, "Mtp3 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp3)));
• DEBUG((EFI_D_INFO, "Mtp4 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp4)));
• DEBUG((EFI_D_INFO, "Mtp5 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp5)));
• DEBUG((EFI_D_INFO, "Mtp6 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp6)));
• DEBUG((EFI_D_INFO, "Mtp7 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp7)));
• DEBUG((EFI_D_INFO, "Mtp8 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp8)));
• DEBUG((EFI_D_INFO, "Mtp9 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp9)));
• DEBUG((EFI_D_INFO, "Mtp10 =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->Mtp10)));
• DEBUG((EFI_D_INFO, "DataErrInjectHi =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectHi)));
• DEBUG((EFI_D_INFO, "DataErrInjectLo =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->DataErrInjectLo)));
• DEBUG((EFI_D_INFO, "EccErrInject =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->EccErrInject)));
• DEBUG((EFI_D_INFO, "CaptureDataHi =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataHi)));
• DEBUG((EFI_D_INFO, "CaptureDataLo =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureDataLo)));
• DEBUG((EFI_D_INFO, "CaptureEcc =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureEcc)));
• DEBUG((EFI_D_INFO, "ErrDetect =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDetect)));
• DEBUG((EFI_D_INFO, "ErrDisable =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrDisable)));
• DEBUG((EFI_D_INFO, "ErrIntEn =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrIntEn)));
• DEBUG((EFI_D_INFO, "CaptureAttributes =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAttributes)));
• DEBUG((EFI_D_INFO, "CaptureAddress =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureAddress)));
• DEBUG((EFI_D_INFO, "CaptureExtAddress =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->CaptureExtAddress)));
• DEBUG((EFI_D_INFO, "ErrSbe =
• 0x%x\n",MmioReadBe32((UINTN)&Ddr->ErrSbe)));
• DEBUG((EFI_D_ERROR,"\n"));

Why the final _ERROR?

This needs to be changed.

...

+}

+/**

• Function to initialize DDR
• **/

+VOID +DramInit (

• )

+{

• struct CcsrDdr *Ddr;
• UINT32 Count, Delay = DDRMC_DELAY;
• Ddr = (VOID *)LS1043A_DDR_ADDR;
• MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG);
• MmioWriteBe32((UINTN)&Ddr->Cs0Bnds, LS1043A_CS0_BNDS);
• MmioWriteBe32((UINTN)&Ddr->Cs0Config, LS1043A_CS0_CONFIG);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg0, LS1043A_TIMING_CFG_0);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg1, LS1043A_TIMING_CFG_1);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg2, LS1043A_TIMING_CFG_2);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg3, LS1043A_TIMING_CFG_3);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg4, LS1043A_TIMING_CFG_4);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg5, LS1043A_TIMING_CFG_5);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg7, LS1043A_TIMING_CFG_7);
• MmioWriteBe32((UINTN)&Ddr->TimingCfg8, LS1043A_TIMING_CFG_8);
• MmioWriteBe32((UINTN)&Ddr->SdramCfg2, LS1043A_DDR_SDRAM_CFG_2);
• MmioWriteBe32((UINTN)&Ddr->SdramMode, LS1043A_DDR_SDRAM_MODE);
• MmioWriteBe32((UINTN)&Ddr->SdramMode2, 0);
• MmioWriteBe32((UINTN)&Ddr->SdramInterval,
• LS1043A_DDR_SDRAM_INTERVAL);
• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl, LS1043A_DDR_WRLVL_CNTL);
• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl2,

LS1043A_DDR_WRLVL_CNTL_2);

...

• MmioWriteBe32((UINTN)&Ddr->DdrWrlvlCntl3, 0);
• MmioWriteBe32((UINTN)&Ddr->DdrCdr1, LS1043A_DDRCDR_1);
• MmioWriteBe32((UINTN)&Ddr->DdrCdr2, LS1043A_DDRCDR_2);
• MmioWriteBe32((UINTN)&Ddr->SdramClkCntl,
• LS1043A_DDR_SDRAM_CLK_CNTL);
• MmioWriteBe32((UINTN)&Ddr->DdrZqCntl, LS1043A_DDR_ZQ_CNTL);
• MmioWriteBe32((UINTN)&Ddr->SdramMode9, LS1043A_DDR_SDRAM_MODE_9);
• MmioWriteBe32((UINTN)&Ddr->SdramMode10, LS1043A_DDR_SDRAM_MODE_10);
• MmioWriteBe32((UINTN)&Ddr->Cs0Config2, 0);
• for(Count = 0; Count < Delay; Count++)

• ;
  

If we are waiting for some operation to take effect, then we badly need at least a MemoryBarrier() here. And if we do, do we still need the delay? If we do need a delay, it is much preferable to use something like gBs->Stall(), or MicroSecondDelay() than just an empty loop.

Ok, will change this in V2.

...

• MmioWriteBe32((UINTN)&Ddr->SdramCfg, LS1043A_DDR_SDRAM_CFG

•                 | LS1043A_DDR_SDRAM_CFG_MEM_EN);
  

• return;

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf new file mode 100644 index 0000000..e8e3aed --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/DdrLib/DdrLib.inf @@ -0,0 +1,41 @@ +#/** DdrLib.inf +# +# Component description file for DdrLib module # # Copyright (c) +2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials # are licensed and +made available under the terms and conditions of the BSD License # +which accompanies this distribution. The full text of the license +may be found at # http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER

EXPRESS OR IMPLIED.

...

+# +#**/

+[Defines]

• INF_VERSION = 0x00010005

0x00010019 if we're following V1.25 of the specification, as published at https://github.com/tianocore/tianocore.github.io/wiki/EDK-II- Specifications

Ok.

...

• BASE_NAME = DdrLib
• FILE_GUID = 8ecefc8f-a2c4-4091-b31f-

20f7aeb0567f

...

• MODULE_TYPE = BASE
• VERSION_STRING = 1.0
• LIBRARY_CLASS = DdrLib

+[Sources.common]

• DdrLib.c

+[LibraryClasses]

• ArmLib
• IoLib
• BaseMemoryLib
• BaseLib
• SocLib

+[Packages]

• EmbeddedPkg/EmbeddedPkg.dec
• MdePkg/MdePkg.dec
• MdeModulePkg/MdeModulePkg.dec
• ArmPlatformPkg/ArmPlatformPkg.dec
• OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec
• OpenPlatformPkg/Chips/Nxp/QoriqLs/NxpQoriqLs.dec

OCD sorting, please?

Ok.

...

-- 1.9.1

Regards, Bhupesh

On 17 October 2016 at 21:04, Bhupesh Sharma bhupesh.sharma@freescale.com wrote:

From: Sakar Arora sakar.arora@nxp.com

NXP/FSL's LS1043A-RDB board houses a CPLD (FPGA) which can be used to control various pin-multiplexing options, which allows certain combinations of peripherals to be enabled on the board.

In addition this CPLD provides a mechanism to divide the NOR/NAND flash memory into primary and alternate regions. While golden images can be flashed on the primary bank, experimental images can be flashed on the alternate bank.

CPLD provides a way to switch from primary to alternate region (and vice-versa), thus protecting the board from damage if primary region is flashed with incorrect set of images.

Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com

---

Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h | 75 +++ Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h | 721 +++++++++++++++++++++ Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c | 157 +++++ .../Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf | 33 + 4 files changed, 986 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf

diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h

Please add this library class to the package .dec file

new file mode 100644 index 0000000..56f47da --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/CpldLib.h @@ -0,0 +1,75 @@ +/** CpldLib.h +* Header defining the LS1043a Cpld specific constants (Base addresses, sizes, flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/

+#ifndef __LS1043A_CPLD_H__ +#define __LS1043A_CPLD_H__

+#include <Library/Common.h>

+/*

• • CPLD register set of LS1043ARDB board-specific.
• */

+struct CpldRegSet {

•   UINT8 CpldVersionMajor; /* 0x0 - CPLD Major Revision Register */
  

•   UINT8 CpldVersionMinor; /* 0x1 - CPLD Minor Revision Register */
  

•   UINT8 PcbaVersion;      /* 0x2 - PCBA Revision Register */
  

•   UINT8 SystemReset;      /* 0x3 - system reset register */
  

•   UINT8 SoftMuxOn;        /* 0x4 - Switch Control Enable Register */
  

•   UINT8 RcwSource1;       /* 0x5 - Reset config word 1 */
  

•   UINT8 RcwSource2;       /* 0x6 - Reset config word 1 */
  

•   UINT8 Vbank;            /* 0x7 - Flash bank selection Control */
  

•   UINT8 SysclkSelect;     /* 0x8 - */
  

•   UINT8 UartSel;          /* 0x9 - */
  

•   UINT8 Sd1RefClkSel;     /* 0xA - */
  

•   UINT8 TdmClkMuxSel;     /* 0xB - */
  

•   UINT8 SdhcSpiCsSel;     /* 0xC - */
  

•   UINT8 StatusLed;        /* 0xD - */
  

•   UINT8 GlobalReset;      /* 0xE - */
  

+};

+/*

• • Reset the board, Reset to alternate bank or Dump registers:
• • RESET - reset to default bank
• • RESET_ALTBANK - reset to alternate bank
• • DUMP_REGISTERS - display the CPLD registers
• */

+typedef enum {

•   RESET = 0,
  

•   RESET_ALTBANK,
  

•   DUMP_REGISTERS
  

+} CpldCmd;

+UINT8 CpldRead(UINTN Reg); +VOID CpldWrite(UINTN Reg, UINT8 Value); +VOID CpldRevBit(UINT8 *Value); +VOID DoCpld (CpldCmd Cmd); +VOID CpldInit (VOID);

+#define CPLD_READ(Reg) CpldRead(offsetof(struct CpldRegSet, Reg)) +#define CPLD_WRITE(Reg, Value) \

•   CpldWrite(offsetof(struct CpldRegSet, Reg), Value)
  

+/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04

+/* SDXC/DSPI CPLD Settings */ +#define ENABLE_SDXC_SOFT_MUX 0x30 +#define ENABLE_RCW_SOFT_MUX 0x01 +#define SELECT_SW4_SDXC 0x40 +#define SELECT_SW5_SDXC 0x01

+#endif diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h b/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h

If this is an internal header, keep it with the .c files. Include/Library should only contain header files that define APIs that are exposed via LibraryClasses

new file mode 100644 index 0000000..27c8295 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/FslIfc.h @@ -0,0 +1,721 @@ +/** @FslIfc.h

• Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#ifndef __FLASH_H__ +#define __FLASH_H__

+#include <Uefi.h>

+#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/PlatformLib.h>

+#include <Protocol/BlockIo.h> +#include <Protocol/Cpu.h>

+#define NOIBR

+#define FSL_IFC_BANK_COUNT 4

+#define NAND_PAGE_SIZE_2K (2048) +#define NAND_SPARE_AREA_SIZE_64B (64) +#define NAND_BLOCK_SIZE_128K (128*1024) +#define NAND_BLOCK_COUNT (2048) +#define NAND_LAST_BLOCK (NAND_BLOCK_COUNT - 1)

+//List of commands. +#define IFC_NAND_CMD_RESET 0xFF +#define IFC_NAND_CMD_READID 0x90

+#define IFC_NAND_CMD_STATUS 0x70

+#define IFC_NAND_CMD_READ0 0x00 +#define IFC_NAND_CMD_READSTART 0x30

+#define IFC_NAND_CMD_ERASE1 0x60 +#define IFC_NAND_CMD_ERASE2 0xD0

+#define IFC_NAND_CMD_SEQIN 0x80 +#define IFC_NAND_CMD_PAGEPROG 0x10

+#define MAX_RETRY_COUNT 150000

+#define FSL_IFC_REG_BASE 0x1530000 +#define FSL_IFC_NAND_BUF_BASE 0x70000000 +#define FSL_IFC_NOR_BUF_BASE 0x60000000

+#define FSL_IFC_NOR_RESERVED_REGION_BASE 0x60700000

+#define FSL_IFC_CSPR_REG_LEN 148 +#define FSL_IFC_AMASK_REG_LEN 144 +#define FSL_IFC_CSOR_REG_LEN 144 +#define FSL_IFC_FTIM_REG_LEN 576

+#define FSL_IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000

+#define FSL_IFC_CSPR_USED_LEN sizeof(FSL_IFC_CSPR) * \

•                                   FSL_IFC_BANK_COUNT
  

+#define FSL_IFC_AMASK_USED_LEN sizeof(FSL_IFC_AMASK) * \

•                                   FSL_IFC_BANK_COUNT
  

+#define FSL_IFC_CSOR_USED_LEN sizeof(FSL_IFC_CSOR) * \

•                                   FSL_IFC_BANK_COUNT
  

+#define FSL_IFC_FTIM_USED_LEN sizeof(FSL_IFC_FTIM) * \

•                                   FSL_IFC_BANK_COUNT
  

+/*

• • NAND Event and Error Status Register (NAND_EVTER_STAT)
• */

+/* Operation Complete */ +#define FSL_IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define FSL_IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define FSL_IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define FSL_IFC_NAND_EVTER_STAT_ECCER 0x02000000

+/*

• • NAND Flash Byte Count Register (NAND_BC)
• */

+/* Byte Count for read/Write */ +#define FSL_IFC_NAND_BC 0x000001FF

+/*

• • NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
• */

+/* NAND Machine specific opcodes OP0-OP14*/ +#define FSL_IFC_NAND_FIR0_OP0 0xFC000000 +#define FSL_IFC_NAND_FIR0_OP0_SHIFT 26 +#define FSL_IFC_NAND_FIR0_OP1 0x03F00000 +#define FSL_IFC_NAND_FIR0_OP1_SHIFT 20 +#define FSL_IFC_NAND_FIR0_OP2 0x000FC000 +#define FSL_IFC_NAND_FIR0_OP2_SHIFT 14 +#define FSL_IFC_NAND_FIR0_OP3 0x00003F00 +#define FSL_IFC_NAND_FIR0_OP3_SHIFT 8 +#define FSL_IFC_NAND_FIR0_OP4 0x000000FC +#define FSL_IFC_NAND_FIR0_OP4_SHIFT 2 +#define FSL_IFC_NAND_FIR1_OP5 0xFC000000 +#define FSL_IFC_NAND_FIR1_OP5_SHIFT 26 +#define FSL_IFC_NAND_FIR1_OP6 0x03F00000 +#define FSL_IFC_NAND_FIR1_OP6_SHIFT 20 +#define FSL_IFC_NAND_FIR1_OP7 0x000FC000 +#define FSL_IFC_NAND_FIR1_OP7_SHIFT 14 +#define FSL_IFC_NAND_FIR1_OP8 0x00003F00 +#define FSL_IFC_NAND_FIR1_OP8_SHIFT 8 +#define FSL_IFC_NAND_FIR1_OP9 0x000000FC +#define FSL_IFC_NAND_FIR1_OP9_SHIFT 2 +#define FSL_IFC_NAND_FIR2_OP10 0xFC000000 +#define FSL_IFC_NAND_FIR2_OP10_SHIFT 26 +#define FSL_IFC_NAND_FIR2_OP11 0x03F00000 +#define FSL_IFC_NAND_FIR2_OP11_SHIFT 20 +#define FSL_IFC_NAND_FIR2_OP12 0x000FC000 +#define FSL_IFC_NAND_FIR2_OP12_SHIFT 14 +#define FSL_IFC_NAND_FIR2_OP13 0x00003F00 +#define FSL_IFC_NAND_FIR2_OP13_SHIFT 8 +#define FSL_IFC_NAND_FIR2_OP14 0x000000FC +#define FSL_IFC_NAND_FIR2_OP14_SHIFT 2

+/*

• • NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
• */

+/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define FSL_IFC_NAND_FCR0_CMD0 0xFF000000 +#define FSL_IFC_NAND_FCR0_CMD0_SHIFT 24 +#define FSL_IFC_NAND_FCR0_CMD1 0x00FF0000 +#define FSL_IFC_NAND_FCR0_CMD1_SHIFT 16 +#define FSL_IFC_NAND_FCR0_CMD2 0x0000FF00 +#define FSL_IFC_NAND_FCR0_CMD2_SHIFT 8 +#define FSL_IFC_NAND_FCR0_CMD3 0x000000FF +#define FSL_IFC_NAND_FCR0_CMD3_SHIFT 0 +#define FSL_IFC_NAND_FCR1_CMD4 0xFF000000 +#define FSL_IFC_NAND_FCR1_CMD4_SHIFT 24 +#define FSL_IFC_NAND_FCR1_CMD5 0x00FF0000 +#define FSL_IFC_NAND_FCR1_CMD5_SHIFT 16 +#define FSL_IFC_NAND_FCR1_CMD6 0x0000FF00 +#define FSL_IFC_NAND_FCR1_CMD6_SHIFT 8 +#define FSL_IFC_NAND_FCR1_CMD7 0x000000FF +#define FSL_IFC_NAND_FCR1_CMD7_SHIFT 0

+/* Timing registers for NAND Flash */

+#define FSL_IFC_FTIM0_NAND_TCCST_SHIFT 25 +#define FSL_IFC_FTIM0_NAND_TCCST(n) ((n) << FSL_IFC_FTIM0_NAND_TCCST_SHIFT) +#define FSL_IFC_FTIM0_NAND_TWP_SHIFT 16 +#define FSL_IFC_FTIM0_NAND_TWP(n) ((n) << FSL_IFC_FTIM0_NAND_TWP_SHIFT) +#define FSL_IFC_FTIM0_NAND_TWCHT_SHIFT 8 +#define FSL_IFC_FTIM0_NAND_TWCHT(n) ((n) << FSL_IFC_FTIM0_NAND_TWCHT_SHIFT) +#define FSL_IFC_FTIM0_NAND_TWH_SHIFT 0 +#define FSL_IFC_FTIM0_NAND_TWH(n) ((n) << FSL_IFC_FTIM0_NAND_TWH_SHIFT) +#define FSL_IFC_FTIM1_NAND_TADLE_SHIFT 24 +#define FSL_IFC_FTIM1_NAND_TADLE(n) ((n) << FSL_IFC_FTIM1_NAND_TADLE_SHIFT) +#define FSL_IFC_FTIM1_NAND_TWBE_SHIFT 16 +#define FSL_IFC_FTIM1_NAND_TWBE(n) ((n) << FSL_IFC_FTIM1_NAND_TWBE_SHIFT) +#define FSL_IFC_FTIM1_NAND_TRR_SHIFT 8 +#define FSL_IFC_FTIM1_NAND_TRR(n) ((n) << FSL_IFC_FTIM1_NAND_TRR_SHIFT) +#define FSL_IFC_FTIM1_NAND_TRP_SHIFT 0 +#define FSL_IFC_FTIM1_NAND_TRP(n) ((n) << FSL_IFC_FTIM1_NAND_TRP_SHIFT) +#define FSL_IFC_FTIM2_NAND_TRAD_SHIFT 21 +#define FSL_IFC_FTIM2_NAND_TRAD(n) ((n) << FSL_IFC_FTIM2_NAND_TRAD_SHIFT) +#define FSL_IFC_FTIM2_NAND_TREH_SHIFT 11 +#define FSL_IFC_FTIM2_NAND_TREH(n) ((n) << FSL_IFC_FTIM2_NAND_TREH_SHIFT) +#define FSL_IFC_FTIM2_NAND_TWHRE_SHIFT 0 +#define FSL_IFC_FTIM2_NAND_TWHRE(n) ((n) << FSL_IFC_FTIM2_NAND_TWHRE_SHIFT) +#define FSL_IFC_FTIM3_NAND_TWW_SHIFT 24 +#define FSL_IFC_FTIM3_NAND_TWW(n) ((n) << FSL_IFC_FTIM3_NAND_TWW_SHIFT)

+/*

• • Flash ROW and COL Address Register (ROWn, COLn)
• */

+/* Main/spare region locator */ +#define FSL_IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define FSL_IFC_NAND_COL_CA_MASK 0x00000FFF

+#define NAND_STATUS_WP 0x80

+/*

• • NAND Event and Error Enable Register (NAND_EVTER_EN)
• */

+/* Operation complete event enable */ +#define FSL_IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define FSL_IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define FSL_IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define FSL_IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define FSL_IFC_NAND_EVTER_EN_ECCER_EN 0x02000000

+/*

• • CSPR - Chip Select Property Register
• */

+#define IFC_CSPR_BA 0xFFFF0000 +#define IFC_CSPR_BA_SHIFT 16 +#define IFC_CSPR_PORT_SIZE 0x00000180 +#define IFC_CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define IFC_CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define IFC_CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define IFC_CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define IFC_CSPR_WP 0x00000040 +#define IFC_CSPR_WP_SHIFT 6 +/* Machine Select */ +#define IFC_CSPR_MSEL 0x00000006 +#define IFC_CSPR_MSEL_SHIFT 1 +/* NOR */ +#define IFC_CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define IFC_CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define IFC_CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define IFC_CSPR_V 0x00000001 +#define IFC_CSPR_V_SHIFT 0

+/*

• • Chip Select Option Register - NOR Flash Mode
• */

+/* Enable Address shift Mode */ +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define IFC_CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000 +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NOR_TRHZ_SHIFT 2 +#define IFC_CSOR_NOR_TRHZ_20 0x00000000 +#define IFC_CSOR_NOR_TRHZ_40 0x00000004 +#define IFC_CSOR_NOR_TRHZ_60 0x00000008 +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C +#define IFC_CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define IFC_CSOR_NOR_BCTLD 0x00000001

+/*

• • Chip Select Option Register FSL_IFC_NAND Machine
• */

+/* Enable ECC Encoder */ +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000 +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define IFC_CSOR_NAND_RAL_MASK 0x01800000 +#define IFC_CSOR_NAND_RAL_SHIFT 20 +#define IFC_CSOR_NAND_RAL_1 0x00000000 +#define IFC_CSOR_NAND_RAL_2 0x00800000 +#define IFC_CSOR_NAND_RAL_3 0x01000000 +#define IFC_CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define IFC_CSOR_NAND_PGS_MASK 0x00180000 +#define IFC_CSOR_NAND_PGS_SHIFT 16 +#define IFC_CSOR_NAND_PGS_512 0x00000000 +#define IFC_CSOR_NAND_PGS_2K 0x00080000 +#define IFC_CSOR_NAND_PGS_4K 0x00100000 +#define IFC_CSOR_NAND_PGS_8K 0x00180000 +/* Spare region Size */ +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000 +#define IFC_CSOR_NAND_SPRZ_SHIFT 13 +#define IFC_CSOR_NAND_SPRZ_16 0x00000000 +#define IFC_CSOR_NAND_SPRZ_64 0x00002000 +#define IFC_CSOR_NAND_SPRZ_128 0x00004000 +#define IFC_CSOR_NAND_SPRZ_210 0x00006000 +#define IFC_CSOR_NAND_SPRZ_218 0x00008000 +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000 +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 +/* Pages Per Block */ +#define IFC_CSOR_NAND_PB_MASK 0x00000700 +#define IFC_CSOR_NAND_PB_SHIFT 8 +#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT +/* Time for Read Enable High to Output High Impedance */ +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NAND_TRHZ_SHIFT 2 +#define IFC_CSOR_NAND_TRHZ_20 0x00000000 +#define IFC_CSOR_NAND_TRHZ_40 0x00000004 +#define IFC_CSOR_NAND_TRHZ_60 0x00000008 +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C +#define IFC_CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define IFC_CSOR_NAND_BCTLD 0x00000001

+#define FSL_IFC_NAND_BUF_MASK 0xffff0000 +#define FSL_IFC_NOR_BUF_MASK 0xffff0000

+#define FSL_IFC_NAND_CSPR ((FSL_IFC_NAND_BUF_BASE & FSL_IFC_NAND_BUF_MASK)\

•                           | IFC_CSPR_PORT_SIZE_8 \
  

•                           | IFC_CSPR_MSEL_NAND \
  

•                           | IFC_CSPR_V)
  

+#define FSL_IFC_NAND_CSPR_EXT 0x0 +#define FSL_IFC_NAND_AMASK 0xFFFF0000 +#define FSL_IFC_NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \

•                            | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  

•                            | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  

•                            | IFC_CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  

•                            | IFC_CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  

•                            | IFC_CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  

•                            | IFC_CSOR_NAND_PB(6))     /* 2^6 Pages Per Block */
  

+/*

• • FTIM0 - NOR Flash Mode
• */

+#define FSL_IFC_FTIM0_NOR 0xF03F3F3F +#define FSL_IFC_FTIM0_NOR_TACSE_SHIFT 28 +#define FSL_IFC_FTIM0_NOR_TACSE(n) ((n) << FSL_IFC_FTIM0_NOR_TACSE_SHIFT) +#define FSL_IFC_FTIM0_NOR_TEADC_SHIFT 16 +#define FSL_IFC_FTIM0_NOR_TEADC(n) ((n) << FSL_IFC_FTIM0_NOR_TEADC_SHIFT) +#define FSL_IFC_FTIM0_NOR_TAVDS_SHIFT 8 +#define FSL_IFC_FTIM0_NOR_TAVDS(n) ((n) << FSL_IFC_FTIM0_NOR_TAVDS_SHIFT) +#define FSL_IFC_FTIM0_NOR_TEAHC_SHIFT 0 +#define FSL_IFC_FTIM0_NOR_TEAHC(n) ((n) << FSL_IFC_FTIM0_NOR_TEAHC_SHIFT) +/*

• • FTIM1 - NOR Flash Mode
• */

+#define FSL_IFC_FTIM1_NOR 0xFF003F3F +#define FSL_IFC_FTIM1_NOR_TACO_SHIFT 24 +#define FSL_IFC_FTIM1_NOR_TACO(n) ((n) << FSL_IFC_FTIM1_NOR_TACO_SHIFT) +#define FSL_IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FSL_IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << FSL_IFC_FTIM1_NOR_TRAD_NOR_SHIFT) +#define FSL_IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FSL_IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FSL_IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/*

• • FTIM2 - NOR Flash Mode
• */

+#define FSL_IFC_FTIM2_NOR 0x0F3CFCFF +#define FSL_IFC_FTIM2_NOR_TCS_SHIFT 24 +#define FSL_IFC_FTIM2_NOR_TCS(n) ((n) << FSL_IFC_FTIM2_NOR_TCS_SHIFT) +#define FSL_IFC_FTIM2_NOR_TCH_SHIFT 18 +#define FSL_IFC_FTIM2_NOR_TCH(n) ((n) << FSL_IFC_FTIM2_NOR_TCH_SHIFT) +#define FSL_IFC_FTIM2_NOR_TWPH_SHIFT 10 +#define FSL_IFC_FTIM2_NOR_TWPH(n) ((n) << FSL_IFC_FTIM2_NOR_TWPH_SHIFT) +#define FSL_IFC_FTIM2_NOR_TWP_SHIFT 0 +#define FSL_IFC_FTIM2_NOR_TWP(n) ((n) << FSL_IFC_FTIM2_NOR_TWP_SHIFT)

+/*

• • FTIM0 - Normal GPCM Mode
• */

+#define FSL_IFC_FTIM0_GPCM 0xF03F3F3F +#define FSL_IFC_FTIM0_GPCM_TACSE_SHIFT 28 +#define FSL_IFC_FTIM0_GPCM_TACSE(n) ((n) << FSL_IFC_FTIM0_GPCM_TACSE_SHIFT) +#define FSL_IFC_FTIM0_GPCM_TEADC_SHIFT 16 +#define FSL_IFC_FTIM0_GPCM_TEADC(n) ((n) << FSL_IFC_FTIM0_GPCM_TEADC_SHIFT) +#define FSL_IFC_FTIM0_GPCM_TAVDS_SHIFT 8 +#define FSL_IFC_FTIM0_GPCM_TAVDS(n) ((n) << FSL_IFC_FTIM0_GPCM_TAVDS_SHIFT) +#define FSL_IFC_FTIM0_GPCM_TEAHC_SHIFT 0 +#define FSL_IFC_FTIM0_GPCM_TEAHC(n) ((n) << FSL_IFC_FTIM0_GPCM_TEAHC_SHIFT) +/*

• • FTIM1 - Normal GPCM Mode
• */

+#define FSL_IFC_FTIM1_GPCM 0xFF003F00 +#define FSL_IFC_FTIM1_GPCM_TACO_SHIFT 24 +#define FSL_IFC_FTIM1_GPCM_TACO(n) ((n) << FSL_IFC_FTIM1_GPCM_TACO_SHIFT) +#define FSL_IFC_FTIM1_GPCM_TRAD_SHIFT 8 +#define FSL_IFC_FTIM1_GPCM_TRAD(n) ((n) << FSL_IFC_FTIM1_GPCM_TRAD_SHIFT) +/*

• • FTIM2 - Normal GPCM Mode
• */

+#define FSL_IFC_FTIM2_GPCM 0x0F3C00FF +#define FSL_IFC_FTIM2_GPCM_TCS_SHIFT 24 +#define FSL_IFC_FTIM2_GPCM_TCS(n) ((n) << FSL_IFC_FTIM2_GPCM_TCS_SHIFT) +#define FSL_IFC_FTIM2_GPCM_TCH_SHIFT 18 +#define FSL_IFC_FTIM2_GPCM_TCH(n) ((n) << FSL_IFC_FTIM2_GPCM_TCH_SHIFT) +#define FSL_IFC_FTIM2_GPCM_TWP_SHIFT 0 +#define FSL_IFC_FTIM2_GPCM_TWP(n) ((n) << FSL_IFC_FTIM2_GPCM_TWP_SHIFT)

+/**

• • fls - find last (most-significant) bit set
• • @x: the word to search
• • This is defined the same way as ffs.
• • Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
• */

+static inline int generic_fls(int x) +{

•   int r = 32;
  

•   if (!x)
  

•           return 0;
  

•   if (!(x & 0xffff0000u)) {
  

•           x <<= 16;
  

•           r -= 16;
  

•   }
  

•   if (!(x & 0xff000000u)) {
  

•           x <<= 8;
  

•           r -= 8;
  

•   }
  

•   if (!(x & 0xf0000000u)) {
  

•           x <<= 4;
  

•           r -= 4;
  

•   }
  

•   if (!(x & 0xc0000000u)) {
  

•           x <<= 2;
  

•           r -= 2;
  

•   }
  

•   if (!(x & 0x80000000u)) {
  

•           x <<= 1;
  

•           r -= 1;
  

•   }
  

•   return r;
  

+}

+static inline int __ilog2(unsigned int x) +{

•   return generic_fls(x) - 1;
  

+}

+/*

• • Address Mask Register
• */

+#define FSL_IFC_AMASK_MASK 0xFFFF0000 +#define FSL_IFC_AMASK_SHIFT 16 +#define FSL_IFC_AMASK(n) (FSL_IFC_AMASK_MASK << \

•                                   (__ilog2(n) - FSL_IFC_AMASK_SHIFT))
  

+#define FSL_IFC_NOR_AMASK FSL_IFC_AMASK(128*1024*1024)

+#define FSL_IFC_NOR_CSPR ((FSL_IFC_NOR_BUF_BASE & FSL_IFC_NOR_BUF_MASK)\

•                           | IFC_CSPR_PORT_SIZE_16 \
  

•                            | IFC_CSPR_MSEL_NOR        \
  

•                            | IFC_CSPR_V)
  

+#define FSL_IFC_NOR_CSPR_EXT 0x0 +#define FSL_IFC_NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \

•                            IFC_CSOR_NOR_TRHZ_80)
  

+#define FSL_IFC_NOR_FTIM0 (FSL_IFC_FTIM0_NOR_TACSE(0x1) | \

•                            FSL_IFC_FTIM0_NOR_TEADC(0x1) | \
  

•                            FSL_IFC_FTIM0_NOR_TAVDS(0x0) | \
  

•                            FSL_IFC_FTIM0_NOR_TEAHC(0xc))
  

+#define FSL_IFC_NOR_FTIM1 (FSL_IFC_FTIM1_NOR_TACO(0x1c) | \

•                            FSL_IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
  

•                            FSL_IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
  

+#define FSL_IFC_NOR_FTIM2 (FSL_IFC_FTIM2_NOR_TCS(0x1) | \

•                            FSL_IFC_FTIM2_NOR_TCH(0x4) | \
  

•                            FSL_IFC_FTIM2_NOR_TWPH(0x8) | \
  

•                            FSL_IFC_FTIM2_NOR_TWP(0x10))
  

+#define FSL_IFC_NOR_FTIM3 0x0

+#define FSL_IFC_NOR_CSPR0 FSL_IFC_NOR_CSPR +#define FSL_IFC_NOR_AMASK0 FSL_IFC_NOR_AMASK +#define FSL_IFC_NOR_CSOR0 FSL_IFC_NOR_CSOR

+#define FSL_IFC_SRAM_BUF_SIZE 0x4000

+/* CPLD */

+/* Convert an address into the right format for the CSPR Registers */ +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)

+#define CPLD_BASE_PHYS LS1043A_CPLD_BASE

+#define FSL_IFC_CPLD_CSPR_EXT (0x0) +#define FSL_IFC_CPLD_CSPR (IFC_CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \

•                           IFC_CSPR_PORT_SIZE_8 | \
  

•                           IFC_CSPR_MSEL_GPCM | \
  

•                           IFC_CSPR_V)
  

+#define FSL_IFC_CPLD_AMASK FSL_IFC_AMASK(64 * 1024) +#define FSL_IFC_CPLD_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \

•                           IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
  

•                           IFC_CSOR_NOR_TRHZ_80)
  

+/* CPLD Timing parameters for IFC GPCM */ +#define FSL_IFC_CPLD_FTIM0 (FSL_IFC_FTIM0_GPCM_TACSE(0xf) | \

•                           FSL_IFC_FTIM0_GPCM_TEADC(0xf) | \
  

•                           FSL_IFC_FTIM0_GPCM_TEAHC(0xf))
  

+#define FSL_IFC_CPLD_FTIM1 (FSL_IFC_FTIM1_GPCM_TACO(0xff) | \

•                           FSL_IFC_FTIM1_GPCM_TRAD(0x3f))
  

+#define FSL_IFC_CPLD_FTIM2 (FSL_IFC_FTIM2_GPCM_TCS(0xf) | \

•                           FSL_IFC_FTIM2_GPCM_TCH(0xf) | \
  

•                           FSL_IFC_FTIM2_GPCM_TWP(0xff))
  

+#define FSL_IFC_CPLD_FTIM3 0x0

+typedef enum {

•   FSL_IFC_CS0 = 0,
  

•   FSL_IFC_CS1,
  

•   FSL_IFC_CS2,
  

•   FSL_IFC_CS3,
  

•   FSL_IFC_CS4,
  

•   FSL_IFC_CS5,
  

•   FSL_IFC_CS6,
  

•   FSL_IFC_CS7,
  

+} FSL_IFC_CHIP_SEL;

+typedef enum {

•   FSL_IFC_FTIM0 = 0,
  

•   FSL_IFC_FTIM1,
  

•   FSL_IFC_FTIM2,
  

•   FSL_IFC_FTIM3,
  

+} FSL_IFC_FTIMS;

+/*

• • Instruction opcodes to be programmed
• • in FIR registers- 6bits
• */

+enum ifc_nand_fir_opcodes {

•   FSL_IFC_FIR_OP_NOP,
  

•   FSL_IFC_FIR_OP_CA0,
  

•   FSL_IFC_FIR_OP_CA1,
  

•   FSL_IFC_FIR_OP_CA2,
  

•   FSL_IFC_FIR_OP_CA3,
  

•   FSL_IFC_FIR_OP_RA0,
  

•   FSL_IFC_FIR_OP_RA1,
  

•   FSL_IFC_FIR_OP_RA2,
  

•   FSL_IFC_FIR_OP_RA3,
  

•   FSL_IFC_FIR_OP_CMD0,
  

•   FSL_IFC_FIR_OP_CMD1,
  

•   FSL_IFC_FIR_OP_CMD2,
  

•   FSL_IFC_FIR_OP_CMD3,
  

•   FSL_IFC_FIR_OP_CMD4,
  

•   FSL_IFC_FIR_OP_CMD5,
  

•   FSL_IFC_FIR_OP_CMD6,
  

•   FSL_IFC_FIR_OP_CMD7,
  

•   FSL_IFC_FIR_OP_CW0,
  

•   FSL_IFC_FIR_OP_CW1,
  

•   FSL_IFC_FIR_OP_CW2,
  

•   FSL_IFC_FIR_OP_CW3,
  

•   FSL_IFC_FIR_OP_CW4,
  

•   FSL_IFC_FIR_OP_CW5,
  

•   FSL_IFC_FIR_OP_CW6,
  

•   FSL_IFC_FIR_OP_CW7,
  

•   FSL_IFC_FIR_OP_WBCD,
  

•   FSL_IFC_FIR_OP_RBCD,
  

•   FSL_IFC_FIR_OP_BTRD,
  

•   FSL_IFC_FIR_OP_RDSTAT,
  

•   FSL_IFC_FIR_OP_NWAIT,
  

•   FSL_IFC_FIR_OP_WFR,
  

•   FSL_IFC_FIR_OP_SBRD,
  

•   FSL_IFC_FIR_OP_UA,
  

•   FSL_IFC_FIR_OP_RB,
  

+};

+typedef struct {

•   UINT32 cspr_ext;
  

•   UINT32 cspr;
  

•   UINT32 res;
  

+} FSL_IFC_CSPR;

+typedef struct {

•   UINT32 amask;
  

•   UINT32 res[0x2];
  

+} FSL_IFC_AMASK;

+typedef struct {

•   UINT32 csor;
  

•   UINT32 csor_ext;
  

•   UINT32 res;
  

+} FSL_IFC_CSOR;

+typedef struct {

•   UINT32 ftim[4];
  

•   UINT32 res[0x8];
  

+}FSL_IFC_FTIM ;

+typedef struct {

•   UINT32 ncfgr;
  

•   UINT32 res1[0x4];
  

•   UINT32 nand_fcr0;
  

•   UINT32 nand_fcr1;
  

•   UINT32 res2[0x8];
  

•   UINT32 row0;
  

•   UINT32 res3;
  

•   UINT32 col0;
  

•   UINT32 res4;
  

•   UINT32 row1;
  

•   UINT32 res5;
  

•   UINT32 col1;
  

•   UINT32 res6;
  

•   UINT32 row2;
  

•   UINT32 res7;
  

•   UINT32 col2;
  

•   UINT32 res8;
  

•   UINT32 row3;
  

•   UINT32 res9;
  

•   UINT32 col3;
  

•   UINT32 res10[0x24];
  

•   UINT32 nand_fbcr;
  

•   UINT32 res11;
  

•   UINT32 nand_fir0;
  

•   UINT32 nand_fir1;
  

•   UINT32 nand_fir2;
  

•   UINT32 res12[0x10];
  

•   UINT32 nand_csel;
  

•   UINT32 res13;
  

•   UINT32 nandseq_strt;
  

•   UINT32 res14;
  

•   UINT32 nand_evter_stat;
  

•   UINT32 res15;
  

•   UINT32 pgrdcmpl_evt_stat;
  

•   UINT32 res16[0x2];
  

•   UINT32 nand_evter_en;
  

•   UINT32 res17[0x2];
  

•   UINT32 nand_evter_intr_en;
  

•   UINT32 res18[0x2];
  

•   UINT32 nand_erattr0;
  

•   UINT32 nand_erattr1;
  

•   UINT32 res19[0x10];
  

•   UINT32 nand_fsr;
  

•   UINT32 res20;
  

•   UINT32 nand_eccstat[4];
  

•   UINT32 res21[0x20];
  

•   UINT32 nanndcr;
  

•   UINT32 res22[0x2];
  

•   UINT32 nand_autoboot_trgr;
  

•   UINT32 res23;
  

•   UINT32 nand_mdr;
  

•   UINT32 res24[0x5C];
  

+} FSL_IFC_NAND;

+/*

• • IFC controller NOR Machine registers
• */

+typedef struct {

•   UINT32 nor_evter_stat;
  

•   UINT32 res1[0x2];
  

•   UINT32 nor_evter_en;
  

•   UINT32 res2[0x2];
  

•   UINT32 nor_evter_intr_en;
  

•   UINT32 res3[0x2];
  

•   UINT32 nor_erattr0;
  

•   UINT32 nor_erattr1;
  

•   UINT32 nor_erattr2;
  

•   UINT32 res4[0x4];
  

•   UINT32 norcr;
  

•   UINT32 res5[0xEF];
  

+} FSL_IFC_NOR;

+/*

• • IFC controller GPCM Machine registers
• */

+typedef struct {

•   UINT32 gpcm_evter_stat;
  

•   UINT32 res1[0x2];
  

•   UINT32 gpcm_evter_en;
  

•   UINT32 res2[0x2];
  

•   UINT32 gpcm_evter_intr_en;
  

•   UINT32 res3[0x2];
  

•   UINT32 gpcm_erattr0;
  

•   UINT32 gpcm_erattr1;
  

•   UINT32 gpcm_erattr2;
  

•   UINT32 gpcm_stat;
  

+} FSL_IFC_GPCM;

+/*

• • IFC Controller Registers
• */

+typedef struct {

•   UINT32 ifc_rev;
  

•   UINT32 res1[0x2];
  

•   FSL_IFC_CSPR cspr_cs[FSL_IFC_BANK_COUNT];
  

•   UINT8 res2[FSL_IFC_CSPR_REG_LEN - FSL_IFC_CSPR_USED_LEN];
  

•   FSL_IFC_AMASK amask_cs[FSL_IFC_BANK_COUNT];
  

•   UINT8 res3[FSL_IFC_AMASK_REG_LEN - FSL_IFC_AMASK_USED_LEN];
  

•   FSL_IFC_CSOR csor_cs[FSL_IFC_BANK_COUNT];
  

•   UINT8 res4[FSL_IFC_CSOR_REG_LEN - FSL_IFC_CSOR_USED_LEN];
  

•   FSL_IFC_FTIM ftim_cs[FSL_IFC_BANK_COUNT];
  

•   UINT8 res5[FSL_IFC_FTIM_REG_LEN - FSL_IFC_FTIM_USED_LEN];
  

•   UINT32 rb_stat;
  

•   UINT32 rb_map;
  

•   UINT32 wp_map;
  

•   UINT32 ifc_gcr;
  

•   UINT32 res7[0x2];
  

•   UINT32 cm_evter_stat;
  

•   UINT32 res8[0x2];
  

•   UINT32 cm_evter_en;
  

•   UINT32 res9[0x2];
  

•   UINT32 cm_evter_intr_en;
  

•   UINT32 res10[0x2];
  

•   UINT32 cm_erattr0;
  

•   UINT32 cm_erattr1;
  

•   UINT32 res11[0x2];
  

•   UINT32 ifc_ccr;
  

•   UINT32 ifc_csr;
  

•   UINT32 ddr_ccr_low;
  

•   UINT32 res12[0x2EA];
  

•   FSL_IFC_NAND ifc_nand;
  

•   FSL_IFC_NOR ifc_nor;
  

•   FSL_IFC_GPCM ifc_gpcm;
  

+} FSL_IFC_REGS;

+VOID IfcNorInit(VOID);

+VOID IfcNandInit(VOID);

+#define FSL_IFC_REGS_BASE \

•   ((FSL_IFC_REGS *)FSL_IFC_REG_BASE)
  

+#endif //__FLASH_H__ diff --git a/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c new file mode 100644 index 0000000..fe115c8 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.c @@ -0,0 +1,157 @@ +/** @CpldLib.c

• Cpld specific Library for LS1043A-RDB board, containing functions to
• program and read the Cpld registers.
• Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
• This program and the accompanying materials
• are licensed and made available under the terms and conditions of the BSD License
• which accompanies this distribution. The full text of the license may be found at
• http://opensource.org/licenses/bsd-license.php
• THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
• WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+**/

+#include <Base.h> +#include <PiPei.h> +#include <Uefi.h>

+#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PrintLib.h> +#include <Library/SerialPortLib.h>

+#include <Library/PlatformLib.h> +#include <Library/CpldLib.h> +#include <Library/FslIfc.h>

+UINT8 +CpldRead (

• OUT UINTN Reg
• )

+{

•   VOID *Base = (VOID *)LS1043A_CPLD_BASE;
  

•   return MmioRead8((UINTN)(Base + Reg));
  

+}

+VOID +CpldWrite (

• IN UINTN Reg,
• IN UINT8 Value
• )

+{

•   VOID *Base = (VOID *)LS1043A_CPLD_BASE;
  

•   MmioWrite8((UINTN)(Base + Reg), Value);
  

+}

+/* Set the boot bank to the alternate bank */ +VOID +CpldSetAlternatebank (

• VOID
• )

+{

•   UINT8 Reg4 = CPLD_READ(SoftMuxOn);
  

•   UINT8 Reg7 = CPLD_READ(Vbank);
  

•   CPLD_WRITE(SoftMuxOn, Reg4 | CPLD_SW_MUX_BANK_SEL);
  

•   Reg7 = (Reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
  

•   CPLD_WRITE(Vbank, Reg7);
  

•   CPLD_WRITE(SystemReset, 1);
  

+}

+/* Set the boot bank to the default bank */ +VOID +CpldSetDefaultBank (

• VOID
• )

+{

•   CPLD_WRITE(GlobalReset, 1);
  

+}

+VOID +CpldDumpRegs (

• VOID
• )

+{

•   DEBUG((EFI_D_INFO, "CpldVersionMajor    = %x\n", CPLD_READ(CpldVersionMajor)));
  

•   DEBUG((EFI_D_INFO, "CpldVersionMinor    = %x\n", CPLD_READ(CpldVersionMinor)));
  

•   DEBUG((EFI_D_INFO, "PcbaVersion = %x\n", CPLD_READ(PcbaVersion)));
  

•   DEBUG((EFI_D_INFO, "SoftMuxOn   = %x\n", CPLD_READ(SoftMuxOn)));
  

•   DEBUG((EFI_D_INFO, "RcwSource1  = %x\n", CPLD_READ(RcwSource1)));
  

•   DEBUG((EFI_D_INFO, "RcwSource2  = %x\n", CPLD_READ(RcwSource2)));
  

•   DEBUG((EFI_D_INFO, "Vbank               = %x\n", CPLD_READ(Vbank)));
  

•   DEBUG((EFI_D_INFO, "SysclkSelect        = %x\n", CPLD_READ(SysclkSelect)));
  

•   DEBUG((EFI_D_INFO, "UartSel     = %x\n", CPLD_READ(UartSel)));
  

•   DEBUG((EFI_D_INFO, "Sd1RefClkSel        = %x\n", CPLD_READ(Sd1RefClkSel)));
  

•   DEBUG((EFI_D_INFO, "TdmClkMuxSel        = %x\n", CPLD_READ(TdmClkMuxSel)));
  

•   DEBUG((EFI_D_INFO, "SdhcSpiCsSel        = %x\n", CPLD_READ(SdhcSpiCsSel)));
  

•   DEBUG((EFI_D_INFO, "StatusLed   = %x\n", CPLD_READ(StatusLed)));
  

+}

+VOID +CpldRevBit (

• OUT UINT8 *Value
• )

+{

•   UINT8 Rev, Val;
  

•   UINTN Index;
  

•   Val = *Value;
  

•   Rev = Val & 1;
  

•   for (Index = 1; Index <= 7; Index++) {
  

•           Val >>= 1;
  

•           Rev <<= 1;
  

•           Rev |= Val & 1;
  

•   }
  

•   *Value = Rev;
  

+}

+VOID +DoCpld (

• IN CpldCmd Cmd
• )

+{

•   switch (Cmd) {
  

•   case RESET:
  

•           CpldSetDefaultBank();
  

•           break;
  

•   case RESET_ALTBANK:
  

•           CpldSetAlternatebank();
  

•           break;
  

•   case DUMP_REGISTERS:
  

•           CpldDumpRegs();
  

•           break;
  

•   default:
  

•           DEBUG((EFI_D_ERROR, "Error: Unknown Cpld Command!\n"));
  

•           break;
  

•   }
  

+}

+VOID +CpldInit (

• VOID
• )

+{

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->cspr_cs[FSL_IFC_CS2].cspr_ext, FSL_IFC_CPLD_CSPR_EXT);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM0],
  

•                   FSL_IFC_CPLD_FTIM0);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM1],
  

•                   FSL_IFC_CPLD_FTIM1);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM2],
  

•                   FSL_IFC_CPLD_FTIM2);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->ftim_cs[FSL_IFC_CS2].ftim[FSL_IFC_FTIM3],
  

•                   FSL_IFC_CPLD_FTIM3);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->csor_cs[FSL_IFC_CS2].csor, FSL_IFC_CPLD_CSOR);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->amask_cs[FSL_IFC_CS2].amask, FSL_IFC_CPLD_AMASK);
  

•   MmioWriteBe32((UINTN) &(FSL_IFC_REGS_BASE)->cspr_cs[FSL_IFC_CS2].cspr, FSL_IFC_CPLD_CSPR);
  

+} diff --git a/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf new file mode 100644 index 0000000..f37d153 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/CpldLib/CpldLib.inf @@ -0,0 +1,33 @@ +#/* @CpldLib.inf +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/

+[Defines]

• INF_VERSION = 0x00010005
• BASE_NAME = CpldLib
• FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b