This patch enables per-interface configuration of used bus width. For this purpose new PCD is added (PcdXenon8BitBusEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 7 ++++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 566884b..297e179 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -12,6 +12,10 @@ PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
Indicates, whether the interface is supplied with 1.8V.
+ gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable + +Indicates, whether the interface is using 8-bit bus. + Examples -------- Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is @@ -19,3 +23,6 @@ supplied with 3.3V and second one with 1.8V:
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1} + +Use 8-bit bus only with first controller: + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x1, 0x0 } diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index f8a1772..57d41c2 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -100,6 +100,7 @@ STATIC UINT8 XenonIdx; // STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); +STATIC UINT8 * CONST Xenon8BitBusEnabled = FixedPcdGetPtr (PcdXenon8BitBusEnable);
// // Prioritized function list to detect card type. @@ -540,6 +541,7 @@ SdMmcPciHcDriverBindingStart ( UINT32 RoutineNum; BOOLEAN Support64BitDma; BOOLEAN Support1v8; + BOOLEAN Support8Bit;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -554,6 +556,7 @@ SdMmcPciHcDriverBindingStart ( // Obtain configuration data for this device and increase index afterwards. // Support1v8 = Xenon1v8Enabled[XenonIdx]; + Support8Bit = Xenon8BitBusEnabled[XenonIdx]; XenonIdx++;
// @@ -645,7 +648,9 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 = 0; }
- Private->Capability[Slot].BusWidth8 = 0; + if (!Support8Bit) { + Private->Capability[Slot].BusWidth8 = 0; + }
if (Private->Capability[Slot].BaseClkFreq == 0) { Private->Capability[Slot].BaseClkFreq = 0xff; diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index b929187..5b5cdd4 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -56,6 +56,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdXenon1v8Enable + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 980697b..efd67b4 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -221,6 +221,7 @@
#SdMmc gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036 + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0 }|VOID*|0x3000037
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}