Hi,
I submit small patchset, which fixes HS200 operation for XenonDxe driver eMMC and also enables PCD-based configuration of each controller's voltage supply, bus width and determine phy operation (so called 'slow mode').
The patches are available publicly in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/opp-...
Any comments or remarks would be welcome.
Best regards, Marcin
Marcin Wojtas (5): Drivers/SdMmc/XenonDxe: Fix HS200 operation Drivers/SdMmc/XenonDxe: Enable supply voltage setting Drivers/SdMmc/XenonDxe: Enable bus width setting Drivers/SdMmc/XenonDxe: Enable 'slow mode' setting Platforms/Marvell/A70x0: Introduce custom board settings for SD/MMC
Documentation/Marvell/PortingGuide/Xenon.txt | 35 +++++++++++++++++++ Drivers/SdMmc/XenonDxe/EmmcDevice.c | 34 ++++-------------- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 52 ++++++++++++++++++++++++---- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 7 ++++ Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ++++++--- Drivers/SdMmc/XenonDxe/XenonSdhci.h | 3 +- Platforms/Marvell/Armada/Armada70x0.dsc | 5 +++ Platforms/Marvell/Marvell.dec | 5 +++ 8 files changed, 117 insertions(+), 40 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Xenon.txt
Following improvements were required: * Set HS_ENABLE bit in HostCtrl1 * Do not disable clock when switching to HS200 mode * Fix HS200 UHS mode value in HostCtrl2 register - Xenon controller uses custom value
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Drivers/SdMmc/XenonDxe/EmmcDevice.c | 34 ++++++---------------------------- 1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..f366038 100755 --- a/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -819,8 +819,8 @@ EmmcSwitchToHS200 ( { EFI_STATUS Status; UINT8 HsTiming; + UINT8 HostCtrl1; UINT8 HostCtrl2; - UINT16 ClockCtrl;
if ((BusWidth != 4) && (BusWidth != 8)) { return EFI_INVALID_PARAMETER; @@ -831,12 +831,10 @@ EmmcSwitchToHS200 ( return Status; } // - // Set to HS200/SDR104 timing - // - // - // Stop bus clock at first + // Set to High Speed timing // - Status = SdMmcHcStopClock (PciIo, Slot); + HostCtrl1 = BIT2; + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { return Status; } @@ -849,33 +847,13 @@ EmmcSwitchToHS200 ( return Status; } // - // Set UHS Mode Select field of Host Control 2 reigster to SDR104 + // Set UHS Mode Select field of Host Control 2 reigster to Xenon-specific HS200 value. // - HostCtrl2 = BIT0 | BIT1; + HostCtrl2 = 0x5; Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2); if (EFI_ERROR (Status)) { return Status; } - // - // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit - // - Status = SdMmcHcWaitMmioSet ( - PciIo, - Slot, - SD_MMC_HC_CLOCK_CTRL, - sizeof (ClockCtrl), - BIT1, - BIT1, - SD_MMC_HC_GENERIC_TIMEOUT - ); - if (EFI_ERROR (Status)) { - return Status; - } - // - // Set SD Clock Enable in the Clock Control register to 1 - // - ClockCtrl = BIT2; - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
HsTiming = 2; Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
On Thu, Jan 05, 2017 at 12:03:37PM +0100, Marcin Wojtas wrote:
Following improvements were required:
- Set HS_ENABLE bit in HostCtrl1
- Do not disable clock when switching to HS200 mode
- Fix HS200 UHS mode value in HostCtrl2 register - Xenon controller uses custom value
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Drivers/SdMmc/XenonDxe/EmmcDevice.c | 34 ++++++---------------------------- 1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..f366038 100755 --- a/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -819,8 +819,8 @@ EmmcSwitchToHS200 ( { EFI_STATUS Status; UINT8 HsTiming;
- UINT8 HostCtrl1; UINT8 HostCtrl2;
- UINT16 ClockCtrl;
if ((BusWidth != 4) && (BusWidth != 8)) { return EFI_INVALID_PARAMETER; @@ -831,12 +831,10 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set to HS200/SDR104 timing
- //
- //
- // Stop bus clock at first
- // Set to High Speed timing //
- Status = SdMmcHcStopClock (PciIo, Slot);
- HostCtrl1 = BIT2;
A descriptive #define for that bit, please.
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { return Status; }
@@ -849,33 +847,13 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set UHS Mode Select field of Host Control 2 reigster to SDR104
- // Set UHS Mode Select field of Host Control 2 reigster to Xenon-specific HS200 value. //
- HostCtrl2 = BIT0 | BIT1;
- HostCtrl2 = 0x5;
And those two.
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2); if (EFI_ERROR (Status)) { return Status; }
- //
- // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
- //
- Status = SdMmcHcWaitMmioSet (
PciIo,Slot,SD_MMC_HC_CLOCK_CTRL,sizeof (ClockCtrl),BIT1,BIT1,SD_MMC_HC_GENERIC_TIMEOUT);- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Set SD Clock Enable in the Clock Control register to 1
- //
- ClockCtrl = BIT2;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
HsTiming = 2;
2 what? And please add the numeric value as a #define in SdMmcPciHci.h.
Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
1.8.3.1
Hi Leif,
2017-01-11 13:28 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:37PM +0100, Marcin Wojtas wrote:
Following improvements were required:
- Set HS_ENABLE bit in HostCtrl1
- Do not disable clock when switching to HS200 mode
- Fix HS200 UHS mode value in HostCtrl2 register - Xenon controller uses custom value
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Drivers/SdMmc/XenonDxe/EmmcDevice.c | 34 ++++++---------------------------- 1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..f366038 100755 --- a/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -819,8 +819,8 @@ EmmcSwitchToHS200 ( { EFI_STATUS Status; UINT8 HsTiming;
- UINT8 HostCtrl1; UINT8 HostCtrl2;
UINT16 ClockCtrl;
if ((BusWidth != 4) && (BusWidth != 8)) { return EFI_INVALID_PARAMETER;
@@ -831,12 +831,10 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set to HS200/SDR104 timing
- //
- //
- // Stop bus clock at first
- // Set to High Speed timing //
- Status = SdMmcHcStopClock (PciIo, Slot);
- HostCtrl1 = BIT2;
A descriptive #define for that bit, please.
Code chunk + comment copied from another function (EmmcSwitchToHighSpeed). Anyway, ok - will fix.
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { return Status; }
@@ -849,33 +847,13 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set UHS Mode Select field of Host Control 2 reigster to SDR104
- // Set UHS Mode Select field of Host Control 2 reigster to Xenon-specific HS200 value. //
- HostCtrl2 = BIT0 | BIT1;
- HostCtrl2 = 0x5;
And those two.
I thought comment can be enough - will fix.
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2); if (EFI_ERROR (Status)) { return Status; }
//
// Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
//
Status = SdMmcHcWaitMmioSet (
PciIo,Slot,SD_MMC_HC_CLOCK_CTRL,sizeof (ClockCtrl),BIT1,BIT1,SD_MMC_HC_GENERIC_TIMEOUT);if (EFI_ERROR (Status)) {
return Status;
}
//
// Set SD Clock Enable in the Clock Control register to 1
//
ClockCtrl = BIT2;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
HsTiming = 2;
2 what? And please add the numeric value as a #define in SdMmcPciHci.h.
This one is not added in the patch - it's original code from edk2. Should I update it anyway?
Best regards, Marcin
On Wed, Jan 11, 2017 at 01:36:29PM +0100, Marcin Wojtas wrote:
@@ -831,12 +831,10 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set to HS200/SDR104 timing
- //
- //
- // Stop bus clock at first
- // Set to High Speed timing //
- Status = SdMmcHcStopClock (PciIo, Slot);
- HostCtrl1 = BIT2;
A descriptive #define for that bit, please.
Code chunk + comment copied from another function (EmmcSwitchToHighSpeed). Anyway, ok - will fix.
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { return Status; }
@@ -849,33 +847,13 @@ EmmcSwitchToHS200 ( return Status; } //
- // Set UHS Mode Select field of Host Control 2 reigster to SDR104
- // Set UHS Mode Select field of Host Control 2 reigster to Xenon-specific HS200 value. //
- HostCtrl2 = BIT0 | BIT1;
- HostCtrl2 = 0x5;
And those two.
I thought comment can be enough - will fix.
With a descriptive define, the comment won't be needed.
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2); if (EFI_ERROR (Status)) { return Status; }
//
// Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
//
Status = SdMmcHcWaitMmioSet (
PciIo,Slot,SD_MMC_HC_CLOCK_CTRL,sizeof (ClockCtrl),BIT1,BIT1,SD_MMC_HC_GENERIC_TIMEOUT);if (EFI_ERROR (Status)) {
return Status;
}
//
// Set SD Clock Enable in the Clock Control register to 1
//
ClockCtrl = BIT2;
Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
HsTiming = 2;
2 what? And please add the numeric value as a #define in SdMmcPciHci.h.
This one is not added in the patch - it's original code from edk2. Should I update it anyway?
Hah, sorry, it just jumped out at me so I didn't spot it didn't have +s. No, you don't have to.
/ Leif
This patch enables per-interface configuration of used power supply. For this purpose new PCD is added (PcdXenon1v8Enable). Implementation required obtaining current controller global index, with help of a PCD already used by PciEmulation driver (PcdPciESdhci), which indicates enabled controllers.
Porting guide documentation for XenonDxe was introduced.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/Xenon.txt | 21 +++++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 40 ++++++++++++++++++++++++---- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 5 ++++ Platforms/Marvell/Marvell.dec | 3 +++ 4 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Xenon.txt
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt new file mode 100644 index 0000000..566884b --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -0,0 +1,21 @@ +XenonDxe porting guide +-------------------- +XenonDxe is a driver supporting SdMmc interface on Marvell platforms. +Following PCDs are required to operate: + + gMarvellTokenSpaceGuid.PcdPciESdhci + +Indication of enabled Xenon controllers. It is common PCD with Marvell +PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt): + + gMarvellTokenSpaceGuid.PcdXenon1v8Enable + +Indicates, whether the interface is supplied with 1.8V. + +Examples +-------- +Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is +supplied with 3.3V and second one with 1.8V: + + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1} diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..f8a1772 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -91,6 +91,17 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = { };
// +// Device global index +// +STATIC UINT8 XenonIdx; + +// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); + +// // Prioritized function list to detect card type. // User could add other card detection logic here. // @@ -528,10 +539,24 @@ SdMmcPciHcDriverBindingStart ( CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; BOOLEAN Support64BitDma; + BOOLEAN Support1v8;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
// + // Set current Xenon device index. + // + while (!XenonDevEnabled[XenonIdx]) { + XenonIdx++; + } + + // + // Obtain configuration data for this device and increase index afterwards. + // + Support1v8 = Xenon1v8Enabled[XenonIdx]; + XenonIdx++; + + // // Open PCI I/O Protocol and save pointer to open protocol // in private data area. // @@ -609,12 +634,17 @@ SdMmcPciHcDriverBindingStart ( Support64BitDma &= Private->Capability[Slot].SysBus64;
// - // Override capabilities structure - only 4 Bit width bus is supported - // by HW and also force using SDR25 mode + // Override capabilities structure according to board configuration. // - Private->Capability[Slot].Sdr104 = 0; - Private->Capability[Slot].Ddr50 = 0; - Private->Capability[Slot].Sdr50 = 0; + if (Support1v8) { + Private->Capability[Slot].Voltage33 = 0; + Private->Capability[Slot].Voltage30 = 0; + } else { + Private->Capability[Slot].Sdr104 = 0; + Private->Capability[Slot].Ddr50 = 0; + Private->Capability[Slot].Sdr50 = 0; + } + Private->Capability[Slot].BusWidth8 = 0;
if (Private->Capability[Slot].BaseClkFreq == 0) { diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index fad9fc6..b929187 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -40,6 +40,7 @@
[Packages] MdePkg/MdePkg.dec + OpenPlatformPkg/Platforms/Marvell/Marvell.dec
[LibraryClasses] BaseLib @@ -52,6 +53,10 @@ UefiLib UefiRuntimeServicesTableLib
+[Pcd] + gMarvellTokenSpaceGuid.PcdPciESdhci + gMarvellTokenSpaceGuid.PcdXenon1v8Enable + [Protocols] gEfiDevicePathProtocolGuid ## TO_START gEfiPciIoProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 313eaa6..980697b 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -219,6 +219,9 @@ gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051
+#SdMmc + gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036 + [Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
On Thu, Jan 05, 2017 at 12:03:38PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used power supply. For this purpose new PCD is added (PcdXenon1v8Enable). Implementation required obtaining current controller global index, with help of a PCD already used by PciEmulation driver (PcdPciESdhci), which indicates enabled controllers.
Porting guide documentation for XenonDxe was introduced.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 21 +++++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 40 ++++++++++++++++++++++++---- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 5 ++++ Platforms/Marvell/Marvell.dec | 3 +++ 4 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Xenon.txt
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt new file mode 100644 index 0000000..566884b --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -0,0 +1,21 @@ +XenonDxe porting guide +-------------------- +XenonDxe is a driver supporting SdMmc interface on Marvell platforms. +Following PCDs are required to operate:
- gMarvellTokenSpaceGuid.PcdPciESdhci
+Indication of enabled Xenon controllers. It is common PCD with Marvell +PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable
+Indicates, whether the interface is supplied with 1.8V.
No ','.
+Examples +-------- +Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is +supplied with 3.3V and second one with 1.8V:
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1}
Inconsistent spacing across the two lines. All existing docs use the spacing used on the first line.
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..f8a1772 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -91,6 +91,17 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = { }; // +// Device global index +// +STATIC UINT8 XenonIdx;
A global variable to keep track of which device we touched last? If there is no other way of dealing with this than a static variable, please at least make it function local. And UINTN/UINT32.
+// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable);
+// // Prioritized function list to detect card type. // User could add other card detection logic here. // @@ -528,10 +539,24 @@ SdMmcPciHcDriverBindingStart ( CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; BOOLEAN Support64BitDma;
- BOOLEAN Support1v8;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); //
- // Set current Xenon device index.
The code looks like what it's actually doing is finding the first enabled Xenon device. The comment should describe the logic it is implementing, the source code already describes the mechanism.
- //
- while (!XenonDevEnabled[XenonIdx]) {
- XenonIdx++;
- }
- //
- // Obtain configuration data for this device and increase index afterwards.
Yes, that's what the code does immediately after. The comment should explain why (or be deleted).
/ Leif
- //
- Support1v8 = Xenon1v8Enabled[XenonIdx];
- XenonIdx++;
- // // Open PCI I/O Protocol and save pointer to open protocol // in private data area. //
@@ -609,12 +634,17 @@ SdMmcPciHcDriverBindingStart ( Support64BitDma &= Private->Capability[Slot].SysBus64; //
- // Override capabilities structure - only 4 Bit width bus is supported
- // by HW and also force using SDR25 mode
- // Override capabilities structure according to board configuration. //
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- if (Support1v8) {
- Private->Capability[Slot].Voltage33 = 0;
- Private->Capability[Slot].Voltage30 = 0;
- } else {
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- }
- Private->Capability[Slot].BusWidth8 = 0;
if (Private->Capability[Slot].BaseClkFreq == 0) { diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index fad9fc6..b929187 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -40,6 +40,7 @@ [Packages] MdePkg/MdePkg.dec
- OpenPlatformPkg/Platforms/Marvell/Marvell.dec
[LibraryClasses] BaseLib @@ -52,6 +53,10 @@ UefiLib UefiRuntimeServicesTableLib +[Pcd]
- gMarvellTokenSpaceGuid.PcdPciESdhci
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START gEfiPciIoProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 313eaa6..980697b 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -219,6 +219,9 @@ gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 +#SdMmc
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} -- 1.8.3.1
On Thu, Jan 05, 2017 at 12:03:38PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used power supply. For this purpose new PCD is added (PcdXenon1v8Enable). Implementation required obtaining current controller global index, with help of a PCD already used by PciEmulation driver (PcdPciESdhci), which indicates enabled controllers.
Porting guide documentation for XenonDxe was introduced.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 21 +++++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 40 ++++++++++++++++++++++++---- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 5 ++++ Platforms/Marvell/Marvell.dec | 3 +++ 4 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Xenon.txt
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt new file mode 100644 index 0000000..566884b --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -0,0 +1,21 @@ +XenonDxe porting guide +-------------------- +XenonDxe is a driver supporting SdMmc interface on Marvell platforms. +Following PCDs are required to operate:
- gMarvellTokenSpaceGuid.PcdPciESdhci
+Indication of enabled Xenon controllers. It is common PCD with Marvell +PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable
+Indicates, whether the interface is supplied with 1.8V.
+Examples +-------- +Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is +supplied with 3.3V and second one with 1.8V:
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1}
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..f8a1772 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -91,6 +91,17 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = { }; // +// Device global index +// +STATIC UINT8 XenonIdx;
+// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable);
Actually, I missed these (they stick out more when subsequent patches add additional ones).
This is not a good way to do this. Map these into a local struct, and call a function initialising the struct from InitializeSdMmcPciHcDxe().
/ Leif
+// // Prioritized function list to detect card type. // User could add other card detection logic here. // @@ -528,10 +539,24 @@ SdMmcPciHcDriverBindingStart ( CARD_TYPE_DETECT_ROUTINE *Routine; UINT32 RoutineNum; BOOLEAN Support64BitDma;
- BOOLEAN Support1v8;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); //
- // Set current Xenon device index.
- //
- while (!XenonDevEnabled[XenonIdx]) {
- XenonIdx++;
- }
- //
- // Obtain configuration data for this device and increase index afterwards.
- //
- Support1v8 = Xenon1v8Enabled[XenonIdx];
- XenonIdx++;
- // // Open PCI I/O Protocol and save pointer to open protocol // in private data area. //
@@ -609,12 +634,17 @@ SdMmcPciHcDriverBindingStart ( Support64BitDma &= Private->Capability[Slot].SysBus64; //
- // Override capabilities structure - only 4 Bit width bus is supported
- // by HW and also force using SDR25 mode
- // Override capabilities structure according to board configuration. //
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- if (Support1v8) {
- Private->Capability[Slot].Voltage33 = 0;
- Private->Capability[Slot].Voltage30 = 0;
- } else {
- Private->Capability[Slot].Sdr104 = 0;
- Private->Capability[Slot].Ddr50 = 0;
- Private->Capability[Slot].Sdr50 = 0;
- }
- Private->Capability[Slot].BusWidth8 = 0;
if (Private->Capability[Slot].BaseClkFreq == 0) { diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index fad9fc6..b929187 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -40,6 +40,7 @@ [Packages] MdePkg/MdePkg.dec
- OpenPlatformPkg/Platforms/Marvell/Marvell.dec
[LibraryClasses] BaseLib @@ -52,6 +53,10 @@ UefiLib UefiRuntimeServicesTableLib +[Pcd]
- gMarvellTokenSpaceGuid.PcdPciESdhci
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START gEfiPciIoProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 313eaa6..980697b 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -219,6 +219,9 @@ gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 +#SdMmc
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} -- 1.8.3.1
Leif,
2017-01-11 14:00 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:38PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used power supply. For this purpose new PCD is added (PcdXenon1v8Enable). Implementation required obtaining current controller global index, with help of a PCD already used by PciEmulation driver (PcdPciESdhci), which indicates enabled controllers.
Porting guide documentation for XenonDxe was introduced.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 21 +++++++++++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 40 ++++++++++++++++++++++++---- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 5 ++++ Platforms/Marvell/Marvell.dec | 3 +++ 4 files changed, 64 insertions(+), 5 deletions(-) create mode 100644 Documentation/Marvell/PortingGuide/Xenon.txt
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt new file mode 100644 index 0000000..566884b --- /dev/null +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -0,0 +1,21 @@ +XenonDxe porting guide +-------------------- +XenonDxe is a driver supporting SdMmc interface on Marvell platforms. +Following PCDs are required to operate:
- gMarvellTokenSpaceGuid.PcdPciESdhci
+Indication of enabled Xenon controllers. It is common PCD with Marvell +PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable
+Indicates, whether the interface is supplied with 1.8V.
+Examples +-------- +Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is +supplied with 3.3V and second one with 1.8V:
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1}
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..f8a1772 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -91,6 +91,17 @@ EMMC_DEVICE_PATH mEmmcDpTemplate = { };
// +// Device global index +// +STATIC UINT8 XenonIdx;
+// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable);
Actually, I missed these (they stick out more when subsequent patches add additional ones).
This is not a good way to do this. Map these into a local struct, and call a function initialising the struct from InitializeSdMmcPciHcDxe().
Ok. When initializing fields of the structure, do you suggest to use FixedPcdGetPtr or PcdGetPtr?
Marcin
On Wed, Jan 11, 2017 at 02:02:50PM +0100, Marcin Wojtas wrote:
// +// Device global index +// +STATIC UINT8 XenonIdx;
+// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable);
Actually, I missed these (they stick out more when subsequent patches add additional ones).
This is not a good way to do this. Map these into a local struct, and call a function initialising the struct from InitializeSdMmcPciHcDxe().
Ok. When initializing fields of the structure, do you suggest to use FixedPcdGetPtr or PcdGetPtr?
It's still a fixed PCD, right?
/ Leif
2017-01-11 16:13 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Wed, Jan 11, 2017 at 02:02:50PM +0100, Marcin Wojtas wrote:
// +// Device global index +// +STATIC UINT8 XenonIdx;
+// +// Tables with used Xenon instances and their configuration +// +STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); +STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable);
Actually, I missed these (they stick out more when subsequent patches add additional ones).
This is not a good way to do this. Map these into a local struct, and call a function initialising the struct from InitializeSdMmcPciHcDxe().
Ok. When initializing fields of the structure, do you suggest to use FixedPcdGetPtr or PcdGetPtr?
It's still a fixed PCD, right?
Right, I was just making sure.
This patch enables per-interface configuration of used bus width. For this purpose new PCD is added (PcdXenon8BitBusEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 7 ++++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 566884b..297e179 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -12,6 +12,10 @@ PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
Indicates, whether the interface is supplied with 1.8V.
+ gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable + +Indicates, whether the interface is using 8-bit bus. + Examples -------- Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is @@ -19,3 +23,6 @@ supplied with 3.3V and second one with 1.8V:
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1} + +Use 8-bit bus only with first controller: + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x1, 0x0 } diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index f8a1772..57d41c2 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -100,6 +100,7 @@ STATIC UINT8 XenonIdx; // STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); +STATIC UINT8 * CONST Xenon8BitBusEnabled = FixedPcdGetPtr (PcdXenon8BitBusEnable);
// // Prioritized function list to detect card type. @@ -540,6 +541,7 @@ SdMmcPciHcDriverBindingStart ( UINT32 RoutineNum; BOOLEAN Support64BitDma; BOOLEAN Support1v8; + BOOLEAN Support8Bit;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -554,6 +556,7 @@ SdMmcPciHcDriverBindingStart ( // Obtain configuration data for this device and increase index afterwards. // Support1v8 = Xenon1v8Enabled[XenonIdx]; + Support8Bit = Xenon8BitBusEnabled[XenonIdx]; XenonIdx++;
// @@ -645,7 +648,9 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 = 0; }
- Private->Capability[Slot].BusWidth8 = 0; + if (!Support8Bit) { + Private->Capability[Slot].BusWidth8 = 0; + }
if (Private->Capability[Slot].BaseClkFreq == 0) { Private->Capability[Slot].BaseClkFreq = 0xff; diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index b929187..5b5cdd4 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -56,6 +56,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdXenon1v8Enable + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 980697b..efd67b4 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -221,6 +221,7 @@
#SdMmc gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036 + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0 }|VOID*|0x3000037
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
On Thu, Jan 05, 2017 at 12:03:39PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used bus width. For this purpose new PCD is added (PcdXenon8BitBusEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 7 ++++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 566884b..297e179 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -12,6 +12,10 @@ PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt): Indicates, whether the interface is supplied with 1.8V.
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
+Indicates, whether the interface is using 8-bit bus.
No ','. What is used if the bus is not 8-bit?
/ Leif
Examples
Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is @@ -19,3 +23,6 @@ supplied with 3.3V and second one with 1.8V: gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{0x0, 0x1}
+Use 8-bit bus only with first controller:
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x1, 0x0 }
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index f8a1772..57d41c2 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -100,6 +100,7 @@ STATIC UINT8 XenonIdx; // STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); +STATIC UINT8 * CONST Xenon8BitBusEnabled = FixedPcdGetPtr (PcdXenon8BitBusEnable); // // Prioritized function list to detect card type. @@ -540,6 +541,7 @@ SdMmcPciHcDriverBindingStart ( UINT32 RoutineNum; BOOLEAN Support64BitDma; BOOLEAN Support1v8;
- BOOLEAN Support8Bit;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -554,6 +556,7 @@ SdMmcPciHcDriverBindingStart ( // Obtain configuration data for this device and increase index afterwards. // Support1v8 = Xenon1v8Enabled[XenonIdx];
- Support8Bit = Xenon8BitBusEnabled[XenonIdx]; XenonIdx++;
// @@ -645,7 +648,9 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 = 0; }
- Private->Capability[Slot].BusWidth8 = 0;
- if (!Support8Bit) {
- Private->Capability[Slot].BusWidth8 = 0;
- }
if (Private->Capability[Slot].BaseClkFreq == 0) { Private->Capability[Slot].BaseClkFreq = 0xff; diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index b929187..5b5cdd4 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -56,6 +56,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdXenon1v8Enable
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index 980697b..efd67b4 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -221,6 +221,7 @@ #SdMmc gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0 }|VOID*|0x3000037
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} -- 1.8.3.1
Hi Leif
2017-01-11 13:46 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:39PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used bus width. For this purpose new PCD is added (PcdXenon8BitBusEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 7 ++++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 566884b..297e179 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -12,6 +12,10 @@ PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
Indicates, whether the interface is supplied with 1.8V.
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
+Indicates, whether the interface is using 8-bit bus.
No ','. What is used if the bus is not 8-bit?
Highest from what SD/MMC can negotiate with card - in EmmcDevice.c configuration is done with 1bit and then there is attempt to switch to 4 or 8 bits, depending on Private->Capability[Slot].BusWidth8 value.
In SdDevice.c however, the field is ignored and the driver attempts always to switch from 1bit to 4bits. In such circumstances, do you wish any changes around this PCD?
Marcin
On Wed, Jan 11, 2017 at 02:05:59PM +0100, Marcin Wojtas wrote:
Hi Leif
2017-01-11 13:46 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:39PM +0100, Marcin Wojtas wrote:
This patch enables per-interface configuration of used bus width. For this purpose new PCD is added (PcdXenon8BitBusEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 7 ++++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Platforms/Marvell/Marvell.dec | 1 + 4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 566884b..297e179 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -12,6 +12,10 @@ PciEmulation driver (see Documentation/Marvell/PortingGuide/PciEmulation.txt):
Indicates, whether the interface is supplied with 1.8V.
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
+Indicates, whether the interface is using 8-bit bus.
No ','. What is used if the bus is not 8-bit?
Highest from what SD/MMC can negotiate with card - in EmmcDevice.c configuration is done with 1bit and then there is attempt to switch to 4 or 8 bits, depending on Private->Capability[Slot].BusWidth8 value.
No, just a clarification of the documentation: "Indicates whether the interface is using an 8-bit bus or (the default) a 4-bit bus."
In SdDevice.c however, the field is ignored and the driver attempts always to switch from 1bit to 4bits. In such circumstances, do you wish any changes around this PCD?
If there is a good reason for that difference in behaviour, then I'd say a further comment of "Note: the SD driver supports a maximum of 4-bit bus and will ignore this setting." is motivated.
/ Leif
Xenon controller comprise PHY, which can be bypassed, using BIT29 of EMMC_PHY_TIMING_ADJUST register. Due to possible hardware issues such operation may have to be enabled in some cases.
This patch enables per-interface configuration of the 'slow mode' usage. For this purpose new PCD is added (PcdXenonSlowModeEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 5 ++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ++++++++++++---- Drivers/SdMmc/XenonDxe/XenonSdhci.h | 3 ++- Platforms/Marvell/Marvell.dec | 1 + 6 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 297e179..159a417 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -16,6 +16,10 @@ Indicates, whether the interface is supplied with 1.8V.
Indicates, whether the interface is using 8-bit bus.
+ gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable + +Indicates, whether the interface is using so called 'slow mode' (PHY bypassing). + Examples -------- Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is @@ -26,3 +30,6 @@ supplied with 3.3V and second one with 1.8V:
Use 8-bit bus only with first controller: gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x1, 0x0 } + +Use 'slow mode' for both controllers: + gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x1, 0x1 } diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 57d41c2..1d5346a 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -101,6 +101,7 @@ STATIC UINT8 XenonIdx; STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); STATIC UINT8 * CONST Xenon8BitBusEnabled = FixedPcdGetPtr (PcdXenon8BitBusEnable); +STATIC UINT8 * CONST XenonSlowModeEnabled = FixedPcdGetPtr (PcdXenonSlowModeEnable);
// // Prioritized function list to detect card type. @@ -542,6 +543,7 @@ SdMmcPciHcDriverBindingStart ( BOOLEAN Support64BitDma; BOOLEAN Support1v8; BOOLEAN Support8Bit; + BOOLEAN SlowMode;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -557,6 +559,7 @@ SdMmcPciHcDriverBindingStart ( // Support1v8 = Xenon1v8Enabled[XenonIdx]; Support8Bit = Xenon8BitBusEnabled[XenonIdx]; + SlowMode = XenonSlowModeEnabled[XenonIdx]; XenonIdx++;
// @@ -672,7 +675,7 @@ SdMmcPciHcDriverBindingStart ( // // Perform Xenon-specific init sequence // - XenonInit (Private); + XenonInit (Private, SlowMode);
// // Initialize HC timeout control diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index 5b5cdd4..c64479b 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -57,6 +57,7 @@ gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdXenon1v8Enable gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable + gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..fe0b564 100755 --- a/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -344,7 +344,8 @@ STATIC VOID XenonSetPhy ( IN EFI_PCI_IO_PROTOCOL *PciIo, - UINT8 Timing + IN UINT8 Timing, + IN BOOLEAN SlowMode ) { UINT32 Var = 0; @@ -368,7 +369,13 @@ XenonSetPhy ( SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var);
// Set SLOW_MODE for PHY - Var |= OUTPUT_QSN_PHASE_SELECT | QSN_PHASE_SLOW_MODE_BIT; + if (SlowMode) { + Var |= QSN_PHASE_SLOW_MODE_BIT; + } + + // Set output clock polarity + Var |= OUTPUT_QSN_PHASE_SELECT; + SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); }
@@ -626,7 +633,8 @@ XenonTransferData (
EFI_STATUS XenonInit ( - IN SD_MMC_HC_PRIVATE_DATA *Private + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN BOOLEAN SlowMode ) { EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo; @@ -646,7 +654,7 @@ XenonInit (
// Set MAX_CLOCK for configuring PHY XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK); - XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50); + XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50, SlowMode);
XenonConfigureInterrupts (PciIo);
diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Drivers/SdMmc/XenonDxe/XenonSdhci.h index 2be0ee6..d22838b 100644 --- a/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -334,7 +334,8 @@ XenonTransferData (
EFI_STATUS XenonInit ( - IN SD_MMC_HC_PRIVATE_DATA *Private + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN BOOLEAN SlowMode );
EFI_STATUS diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index efd67b4..f011de1 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -222,6 +222,7 @@ #SdMmc gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036 gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0 }|VOID*|0x3000037 + gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x0 }|VOID*|0x3000038
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
On Thu, Jan 05, 2017 at 12:03:40PM +0100, Marcin Wojtas wrote:
Xenon controller comprise PHY,
"comprise" -> "contains a".
which can be bypassed, using BIT29 of EMMC_PHY_TIMING_ADJUST register.
Calling out bit numbers in a commit message is a bit too much detail. Just say it can be disabled through that register.
Due to possible hardware issues such operation may have to be enabled in some cases.
This patch enables per-interface configuration of the 'slow mode' usage. For this purpose new PCD is added (PcdXenonSlowModeEnable). Porting guide documentation is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Documentation/Marvell/PortingGuide/Xenon.txt | 7 +++++++ Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 5 ++++- Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf | 1 + Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ++++++++++++---- Drivers/SdMmc/XenonDxe/XenonSdhci.h | 3 ++- Platforms/Marvell/Marvell.dec | 1 + 6 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/Documentation/Marvell/PortingGuide/Xenon.txt b/Documentation/Marvell/PortingGuide/Xenon.txt index 297e179..159a417 100644 --- a/Documentation/Marvell/PortingGuide/Xenon.txt +++ b/Documentation/Marvell/PortingGuide/Xenon.txt @@ -16,6 +16,10 @@ Indicates, whether the interface is supplied with 1.8V. Indicates, whether the interface is using 8-bit bus.
- gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable
+Indicates, whether the interface is using so called 'slow mode' (PHY bypassing).
Examples
Assuming we want to enable both SdMmc ports on Armada 70x0 board, first one is @@ -26,3 +30,6 @@ supplied with 3.3V and second one with 1.8V: Use 8-bit bus only with first controller: gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x1, 0x0 }
+Use 'slow mode' for both controllers:
- gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x1, 0x1 }
diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 57d41c2..1d5346a 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -101,6 +101,7 @@ STATIC UINT8 XenonIdx; STATIC UINT8 * CONST XenonDevEnabled = FixedPcdGetPtr (PcdPciESdhci); STATIC UINT8 * CONST Xenon1v8Enabled = FixedPcdGetPtr (PcdXenon1v8Enable); STATIC UINT8 * CONST Xenon8BitBusEnabled = FixedPcdGetPtr (PcdXenon8BitBusEnable); +STATIC UINT8 * CONST XenonSlowModeEnabled = FixedPcdGetPtr (PcdXenonSlowModeEnable); // // Prioritized function list to detect card type. @@ -542,6 +543,7 @@ SdMmcPciHcDriverBindingStart ( BOOLEAN Support64BitDma; BOOLEAN Support1v8; BOOLEAN Support8Bit;
- BOOLEAN SlowMode;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); @@ -557,6 +559,7 @@ SdMmcPciHcDriverBindingStart ( // Support1v8 = Xenon1v8Enabled[XenonIdx]; Support8Bit = Xenon8BitBusEnabled[XenonIdx];
- SlowMode = XenonSlowModeEnabled[XenonIdx];
This is also starting to stick out a bit.
Could you instead move the increment of XenonIdx later in function and create a macro. Given a global struct called Config, you could do something like:
#define FEATURE_ENABLED(x, y) (Config.Xenon ## x ## Enabled[y])
And then inline
XenonIdx++; // @@ -672,7 +675,7 @@ SdMmcPciHcDriverBindingStart ( // // Perform Xenon-specific init sequence //
- XenonInit (Private);
- XenonInit (Private, SlowMode);
XenonInit (Private, FEATURE_ENABLED (SlowMode));
?
And adapt preceding patches to the same format?
/ Leif
// // Initialize HC timeout control diff --git a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf index 5b5cdd4..c64479b 100644 --- a/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf +++ b/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.inf @@ -57,6 +57,7 @@ gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdXenon1v8Enable gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable
- gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable
[Protocols] gEfiDevicePathProtocolGuid ## TO_START diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..fe0b564 100755 --- a/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -344,7 +344,8 @@ STATIC VOID XenonSetPhy ( IN EFI_PCI_IO_PROTOCOL *PciIo,
- UINT8 Timing
- IN UINT8 Timing,
- IN BOOLEAN SlowMode )
{ UINT32 Var = 0; @@ -368,7 +369,13 @@ XenonSetPhy ( SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); // Set SLOW_MODE for PHY
- Var |= OUTPUT_QSN_PHASE_SELECT | QSN_PHASE_SLOW_MODE_BIT;
- if (SlowMode) {
Var |= QSN_PHASE_SLOW_MODE_BIT;- }
- // Set output clock polarity
- Var |= OUTPUT_QSN_PHASE_SELECT;
- SdMmcHcRwMmio(PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, FALSE, SDHC_REG_SIZE_4B, &Var); }
@@ -626,7 +633,8 @@ XenonTransferData ( EFI_STATUS XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN BOOLEAN SlowMode )
{ EFI_PCI_IO_PROTOCOL *PciIo = Private->PciIo; @@ -646,7 +654,7 @@ XenonInit ( // Set MAX_CLOCK for configuring PHY XenonSetClk (PciIo, Private, XENON_MMC_MAX_CLK);
- XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50);
- XenonSetPhy (PciIo, MMC_TIMING_UHS_SDR50, SlowMode);
XenonConfigureInterrupts (PciIo); diff --git a/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Drivers/SdMmc/XenonDxe/XenonSdhci.h index 2be0ee6..d22838b 100644 --- a/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -334,7 +334,8 @@ XenonTransferData ( EFI_STATUS XenonInit (
- IN SD_MMC_HC_PRIVATE_DATA *Private
- IN SD_MMC_HC_PRIVATE_DATA *Private,
- IN BOOLEAN SlowMode );
EFI_STATUS diff --git a/Platforms/Marvell/Marvell.dec b/Platforms/Marvell/Marvell.dec index efd67b4..f011de1 100644 --- a/Platforms/Marvell/Marvell.dec +++ b/Platforms/Marvell/Marvell.dec @@ -222,6 +222,7 @@ #SdMmc gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0 }|VOID*|0x3000036 gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0 }|VOID*|0x3000037
- gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x0 }|VOID*|0x3000038
[Protocols] gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} -- 1.8.3.1
This commit adds following Xenon custom configuration for Armada 70x0 board after it was enabled in the driver:
* AP HW block Xenon controller: - 3.3V power supply - 4-bit bus width - 'slow mode' enabled
* CP0 HW block Xenon controller: - 1.8V power supply - 4-bit bus width - 'slow mode' disabled
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com --- Platforms/Marvell/Armada/Armada70x0.dsc | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 134ab71..8b554a4 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -150,3 +150,8 @@
#SATA gMarvellTokenSpaceGuid.PcdSataBaseAddress|0xF2540000 + + #SdMmc + gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x1, 0x0 }
On Thu, Jan 05, 2017 at 12:03:41PM +0100, Marcin Wojtas wrote:
This commit adds following Xenon custom configuration for Armada 70x0 board after it was enabled in the driver:
AP HW block Xenon controller:
- 3.3V power supply
- 4-bit bus width
- 'slow mode' enabled
CP0 HW block Xenon controller:
- 1.8V power supply
- 4-bit bus width
- 'slow mode' disabled
Just to clarify - so even though we add 8-bit bus support, we don't have a way to test it yet?
/ Leif
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas mw@semihalf.com
Platforms/Marvell/Armada/Armada70x0.dsc | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/Platforms/Marvell/Armada/Armada70x0.dsc b/Platforms/Marvell/Armada/Armada70x0.dsc index 134ab71..8b554a4 100644 --- a/Platforms/Marvell/Armada/Armada70x0.dsc +++ b/Platforms/Marvell/Armada/Armada70x0.dsc @@ -150,3 +150,8 @@ #SATA gMarvellTokenSpaceGuid.PcdSataBaseAddress|0xF2540000
- #SdMmc
- gMarvellTokenSpaceGuid.PcdXenon1v8Enable|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdXenon8BitBusEnable|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdXenonSlowModeEnable|{ 0x1, 0x0 }
-- 1.8.3.1
Leif,
2017-01-11 14:11 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:41PM +0100, Marcin Wojtas wrote:
This commit adds following Xenon custom configuration for Armada 70x0 board after it was enabled in the driver:
AP HW block Xenon controller:
- 3.3V power supply
- 4-bit bus width
- 'slow mode' enabled
CP0 HW block Xenon controller:
- 1.8V power supply
- 4-bit bus width
- 'slow mode' disabled
Just to clarify - so even though we add 8-bit bus support, we don't have a way to test it yet?
Not yet, but I'm going to submit new SoC support (Armada80x0), where it's used.
On Wed, Jan 11, 2017 at 03:05:03PM +0100, Marcin Wojtas wrote:
2017-01-11 14:11 GMT+01:00 Leif Lindholm leif.lindholm@linaro.org:
On Thu, Jan 05, 2017 at 12:03:41PM +0100, Marcin Wojtas wrote:
This commit adds following Xenon custom configuration for Armada 70x0 board after it was enabled in the driver:
AP HW block Xenon controller:
- 3.3V power supply
- 4-bit bus width
- 'slow mode' enabled
CP0 HW block Xenon controller:
- 1.8V power supply
- 4-bit bus width
- 'slow mode' disabled
Just to clarify - so even though we add 8-bit bus support, we don't have a way to test it yet?
Not yet, but I'm going to submit new SoC support (Armada80x0), where it's used.
Which is OK, just wanted to make sure it wasn't a typo.
/ Leif
-
Leif Lindholm -
Marcin Wojtas