Follow chip team suggestion, HCCS(Huawei Cache-Coherent System) may be unstable while speed is 3.0G, so use 2.6G to avoid some unstable stress issue.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org --- Silicon/Hisilicon/Include/Library/OemMiscLib.h | 10 ++++++++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++ 2 files changed, 18 insertions(+)
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h index dfac87d635d9..ea95fe38d75c 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,6 +22,11 @@ #include <PlatformArch.h> #include <Library/I2CLib.h>
+#define HCCS_PLL_VALUE_2600 0x52240681 +#define HCCS_PLL_VALUE_2800 0x52240701 +#define HCCS_PLL_VALUE_3000 0x52240781 + + #define PCIEDEVICE_REPORT_MAX 8 #define MAX_PROCESSOR_SOCKETS MAX_SOCKET #define MAX_MEMORY_CHANNELS MAX_CHANNEL @@ -55,4 +60,9 @@ extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM]; EFI_HII_HANDLE EFIAPI OemGetPackages (); UINTN OemGetCpuFreq (UINT8 Socket);
+UINTN +OemGetHccsFreq ( + VOID + ); + #endif diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c index 624fa33d2e14..914387de7d63 100644 --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -223,3 +223,11 @@ UINTN OemGetCpuFreq (UINT8 Socket) } }
+UINTN +OemGetHccsFreq ( + VOID + ) +{ + return HCCS_PLL_VALUE_2600; +} +