From: Sakar Arora sakar.arora@nxp.com
This patch adds the basic support for NXP/FSL's LS1043A RDB board. LS1043A RDB board supports a number of on-board peripherals. This patch adds the basic framework for the same.
Further details about this board can be seen here: http://www.nxp.com/products/microcontrollers-and-processors/ arm-processors/qoriq-arm-processors/qoriq-ls1043a-reference-design-board:LS1043A-RDB
Signed-off-by: Sakar Arora sakar.arora@nxp.com Signed-off-by: Bhupesh Sharma bhupesh.sharma@nxp.com --- Platforms/Nxp/LS1043aRdb/Include/Library/Common.h | 68 ++++++++ .../Nxp/LS1043aRdb/Include/Library/PlatformLib.h | 178 +++++++++++++++++++++ .../Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c | 103 ++++++++++++ .../LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c | 107 +++++++++++++ .../Library/LS1043aRdbLib/LS1043aRdbHelper.S | 61 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbLib.inf | 56 +++++++ .../Library/LS1043aRdbLib/LS1043aRdbMem.c | 149 +++++++++++++++++ 7 files changed, 722 insertions(+) create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/Common.h create mode 100644 Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf create mode 100644 Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c
diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h new file mode 100644 index 0000000..192a249 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/Common.h @@ -0,0 +1,68 @@ +/** @Common.h + Header defining the General Purpose Utilities + + Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __COMMON_H__ +#define __COMMON_H__ + + + +#define DMA_MINALIGN 64 + +#define offsetof(TYPE, MEMBER) ((UINTN) &((TYPE *)0)->MEMBER) + + +typedef UINTN PhysAddrT; +typedef UINTN PhysSizeT; + +static inline PhysAddrT VirtToPhys(VOID * VAddr) +{ + return (PhysAddrT)(VAddr); +} + +/* + * The ALLOC_CACHE_ALIGN_BUF macro is used to allocate a buffer + * that meets the minimum architecture alignment requirements for DMA. + * + * The resulting buffer is aligned to the value of DMA_MINALIGN. + * + * The buffer variable created is a pointer to the specified type, and + * NOT an array. + * + * The size parameter is the number of array elements to allocate. + */ + +#define ALIGN_BUFF(x,a) ALIGN_MSK((x),(typeof(x))(a)-1) +#define ALIGN_MSK(x,mask) (((x)+(mask))&~(mask)) + +#define PAD_CNT(S, Pad) (((S) - 1) / (Pad) + 1) +#define PAD_SIZE(S, Pad) (PAD_CNT(S, Pad) * Pad) + +#define ROUND_OFF(a,b) (((a) + (b) - 1) & ~((b) - 1)) + +#define DMA_MINALIGN 64 + +#define ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, Pad) \ + INT8 __##Name[ROUND_OFF(PAD_SIZE((Size) * sizeof(Type), Pad), Align) \ + + (Align - 1)]; \ + \ + Type *Name = (Type *) ALIGN_BUFF((UINTN)__##Name, Align) +#define ALLOC_ALIGN_BUF(Type, Name, Size, Align) \ + ALLOC_ALIGN_BUF_PAD(Type, Name, Size, Align, 1) +#define ALLOC_CACHE_ALIGN_BUF_PAD(Type, Name, Size, Pad) \ + ALLOC_ALIGN_BUF_PAD(Type, Name, size, DMA_MINALIGN, Pad) +#define ALLOC_CACHE_ALIGN_BUF(Type, Name, Size) \ + ALLOC_ALIGN_BUF(Type, Name, Size, DMA_MINALIGN) + +#endif diff --git a/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h new file mode 100644 index 0000000..39247e8 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Include/Library/PlatformLib.h @@ -0,0 +1,178 @@ +/** LS1043aRdb.h +* Header defining the LS1043aRdb constants (Base addresses, sizes, flags) +* +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __LS1043aRDB_PLATFORM_H__ +#define __LS1043aRDB_PLATFORM_H__ + +// Types +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +#define LS1043A_CACHELINE_SIZE 32 + +#define LS1043A_SECURE_BOOTROM_BASE_ADDR 0x00000000 +#define LS1043A_SECURE_BOOTROM_SIZE 0x00100000 /* 1MB */ +#define LS1043A_EXT_BOOTROM_BASE_ADDR 0x00100000 +#define LS1043A_EXT_BOOTROM_SIZE 0x00F00000 /* 15MB */ +#define LS1043A_CCSR_BASE_ADDR 0x01000000 +#define LS1043A_CCSR_SIZE 0x0F000000 /* 240MB */ + #define LS1043A_IMMR 0x01000000 + #define LS1043A_DDR_ADDR 0x01080000 + #define LS1043A_DSPI_ADDR 0x02100000 + #define LS1043A_SDXC_ADDR 0x01560000 + #define LS1043A_CCI400_ADDR (LS1043A_IMMR + 0x00180000) + #define LS1043A_TZASC380_ADDR (LS1043A_IMMR + 0x00500000) + #define LS1043A_CSU_ADDR (LS1043A_IMMR + 0x00510000) + #define LS1043A_GUTS_ADDR (LS1043A_IMMR + 0x00ee0000) + #define LS1043A_CLK_ADDR (LS1043A_IMMR + 0x00ee1000) + #define LS1043A_FMAN_ADDR (LS1043A_IMMR + 0x00a00000) + #define LS1043A_BMAN_ADDR (LS1043A_IMMR + 0x00890000) + #define LS1043A_QMAN_ADDR (LS1043A_IMMR + 0x00880000) + #define GIC_BASE_ADDR 0x01402000 + #define GIC_SIZE 0x1000 + #define GICDIST_BASE_ADDR 0x01401000 + #define GICDIST_SIZE 0x1000 + #define DUART1_BASE_ADDR 0x21C0000 + #define DUART1_SIZE 0x1000 + #define DUART2_BASE_ADDR 0x21D0000 + #define DUART2_SIZE 0x1000 + #define WDOG1_BASE_ADDR 0x02AD0000 + #define WDOG2_BASE_ADDR 0x02AE0000 + #define WDOG3_BASE_ADDR 0x02A70000 + #define WDOG4_BASE_ADDR 0x02A80000 + #define WDOG5_BASE_ADDR 0x02A90000 + #define WDOG_SIZE 0x1000 + #define WDOG_WCR_OFFSET 0 + #define WDOG_WSR_OFFSET 2 + #define WDOG_WRSR_OFFSET 4 + #define WDOG_WICR_OFFSET 6 + #define WDOG_WCR_WT (0xFF << 8) + #define WDOG_WCR_WDE (1 << 2) + #define WDOG_SERVICE_SEQ1 0x5555 + #define WDOG_SERVICE_SEQ2 0xAAAA + #define WDOG_WCR_WDZST 0x1 + #define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */ + + #define I2C0_BASE_ADDRESS 0x02180000 + #define I2C1_BASE_ADDRESS 0x02190000 + #define I2C2_BASE_ADDRESS 0x021A0000 + #define I2C3_BASE_ADDRESS 0x02183000 + #define I2C_SIZE 0x10000 + #define DSPI_MEMORY_SIZE 0x10000 + #define DDRC_MEMORY_SIZE 0x10000 + #define SDXC_MEMORY_SIZE 0x10000 + #define LS1043A_TIMER_ADDR 0x02b00000 + #define IFC_REG_BASE_ADDR 0x1530000 + #define IFC_REG_SIZE 0x0003000 + #define SCFG_BASE_ADDR 0x1570000 + #define SCFG_SIZE 0x0010000 + +/* SMMU Defintions */ +#define SMMU_BASE_ADDR 0x09000000 +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) + +#define SCR0_USFCFG_MASK 0x00000400 +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SACR_PAGESIZE_MASK 0x00010000 +#define IDR1_PAGESIZE_MASK 0x80000000 + +#define LS1043A_OCRAM1_BASE_ADDR 0x10000000 +#define LS1043A_OCRAM1_SIZE 0x00010000 /* 64KB */ +#define LS1043A_OCRAM2_BASE_ADDR 0x10010000 +#define LS1043A_OCRAM2_SIZE 0x00010000 /* 64KB */ +#define LS1043A_STM_BASE_ADDR 0x12000000 +#define LS1043A_STM_SIZE 0x01000000 /* 16MB */ +#define LS1043A_DCSR_BASE_ADDR 0x20000000 +#define LS1043A_DCSR_SIZE 0x04000000 /* 64MB */ +#define LS1043A_QSPI_BASE_ADDR 0x40000000 +#define LS1043A_QSPI_SIZE 0x20000000 /* 512MB */ +#define LS1043A_IFC_REGION1_BASE_ADDR 0x60000000 +#define LS1043A_IFC_REGION1_BASE_SIZE 0x20000000 /* 512MB */ +#define LS1043A_DRAM1_BASE_ADDR 0x0080000000 +#define LS1043A_DRAM1_SIZE 0x0080000000 /* 2GB */ +#define LS1043A_QMAN_SWP_BASE_ADDR 0x0500000000 +#define LS1043A_QMAN_SWP_SIZE 0x0080000000 /* 128MB */ +#define LS1043A_BMAN_SWP_BASE_ADDR 0x0508000000 +#define LS1043A_BMAN_SWP_SIZE 0x0080000000 /* 128MB */ +#define LS1043A_IFC_REGION2_BASE_ADDR 0x0620000000 +#define LS1043A_IFC_REGION2_BASE_SIZE 0x00E0000000 /* 3.5GB */ +#define LS1043A_DRAM2_BASE_ADDR 0x0880000000 +#define LS1043A_DRAM2_SIZE 0x0780000000 /* 30GB */ +#define LS1043A_SERDES_ADDR (LS1043A_IMMR + 0xEA0000) +#define LS1043A_SRDS_1 +#define LS1043A_PCI_EXP1_BASE_ADDR 0x4000000000 +#define LS1043A_PCI_EXP1_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_PCI_EXP2_BASE_ADDR 0x4800000000 +#define LS1043A_PCI_EXP2_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_PCI_EXP3_BASE_ADDR 0x5000000000 +#define LS1043A_PCI_EXP3_BASE_SIZE 0x800000000 /* 32GB */ +#define LS1043A_DRAM3_BASE_ADDR 0x8800000000 +#define LS1043A_DRAM3_SIZE 0x7800000000 /* 480GB */ + +/* + * CPLD + */ +#define LS1043A_CPLD_BASE 0x7fb00000 + +/* + * Global defines + */ +#define NOR_BOOT 0x0 +#define NAND_BOOT 0x1 +#define SD_BOOT 0x2 + +/* PCI controllers addresses */ +#define LS1043A_PCIE1_PHYS_BASE 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_BASE 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_BASE 0x5000000000ULL + +#define LS1043A_PCIE1_PHYS_ADDR 0x5000000000ULL +#define LS1043A_PCIE2_PHYS_ADDR 0x4800000000ULL +#define LS1043A_PCIE3_PHYS_ADDR 0x5000000000ULL + +#define LS1043A_PCIE1_ADDR 0x03600000 +#define LS1043A_PCIE2_ADDR 0x03500000 +#define LS1043A_PCIE3_ADDR 0x03600000 + +/* PCIe */ +#define LS1043A_LS_PCI /* Enable PCI/PCIE */ +#define LS1043A_LS_PCIE1 /* PCIE controler 1 */ +#define LS1043A_LS_PCIE2 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE3 /* PCIE controler 2 */ +#define LS1043A_LS_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ + +#define LS1043A_LS_PCI_64BIT + +#define LS1043A_LS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define LS1043A_LS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define LS1043A_LS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define LS1043A_LS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define LS1043A_LS_PCIE_IO_BUS 0x00000000 +#define LS1043A_LS_PCIE_IO_PHYS_OFF 0x00010000 +#define LS1043A_LS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define LS1043A_LS_PCIE_MEM_BUS 0x40000000 +#define LS1043A_LS_PCIE_MEM_PHYS_OFF 0x40000000 +#define LS1043A_LS_PCIE_MEM_SIZE 0x40000000 /* 1 GB */ + +#endif diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c new file mode 100644 index 0000000..7159749 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/Common.c @@ -0,0 +1,103 @@ +/** Common.c +* +* Copyright (c) 2016, Freescale Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/PlatformLib.h> +#include <Library/DebugLib.h> + +UINT32 +__Div64_32 ( + IN UINT64 *N, + IN UINT32 Base + ) +{ + UINT64 Rem = *N; + UINT64 b = Base; + UINT64 Res, d = 1; + UINT32 High = Rem >> 32; + + /** Reduce the thing a bit first */ + Res = 0; + if (High >= Base) { + High /= Base; + Res = (UINT64) High << 32; + Rem -= (UINT64) (High*Base) << 32; + } + + while ((UINTN)b > 0 && b < Rem) { + b = b+b; + d = d+d; + } + + do { + if (Rem >= b) { + Rem -= b; + Res += d; + } + b >>= 1; + d >>= 1; + } while (d); + + *N = Res; + return Rem; +} + +/* + * PrINT32 Sizes As "Xxx KiB", "Xxx.Y KiB", "Xxx MiB", "Xxx.Y MiB", + * Xxx GiB, Xxx.Y GiB, Etc As Needed; Allow for Optional Trailing String + * (Like "\n") + */ +VOID +PrintSize ( + IN UINT64 Size, + IN CONST INT8 *S + ) +{ + UINT64 M = 0, N; + UINT64 F; + static CONST INT8 Names[] = {'E', 'P', 'T', 'G', 'M', 'K'}; + UINT64 D = 10 * ARRAY_SIZE(Names); + CHAR8 C = 0; + UINT32 I; + + for (I = 0; I < ARRAY_SIZE(Names); I++, D -= 10) { + if (Size >> D) { + C = Names[I]; + break; + } + } + + if (!C) { + DEBUG((EFI_D_ERROR, "%Ld Bytes,\n %a", Size, S)); + return; + } + + N = Size >> D; + F = Size & ((1ULL << D) - 1); + + /* if There'S A Remainder, Deal With It */ + if (F) { + M = (10ULL * F + (1ULL << (D - 1))) >> D; + + if (M >= 10) { + M -= 10; + N += 1; + } + } + + DEBUG((EFI_D_ERROR, "%Ld", N)); + if (M) { + DEBUG((EFI_D_ERROR, ".%Ld", M)); + } + DEBUG((EFI_D_ERROR, " %ciB, %a ", C, S)); +} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c new file mode 100644 index 0000000..4fcb8a3 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdb.c @@ -0,0 +1,107 @@ +/** LS1043aRdb.c +* +* RDB specific Library for LS1043A SoC, containing functions to initialize +* RDB boards. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Ppi/ArmMpCoreInfo.h> +#include <Library/PlatformLib.h> + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(LS1043aMpCoreInfoCTA53x4) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = LS1043aMpCoreInfoCTA53x4; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S new file mode 100644 index 0000000..5d9807f --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbHelper.S @@ -0,0 +1,61 @@ +# @file +# +# Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S +# +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include <AsmMacroIoLib.h> +#include <AsmMacroIoLibV8.h> +#include <AutoGen.h> + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) + +GCC_ASM_IMPORT(ArmReadMpidr) + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + and x1, x0, #3 + mov x0, #0 + cbnz x1, 1f + mov x0, #1 +1: + ret + +ASM_PFX(ArmPlatformPeiBootAction): +EL1_OR_EL2_OR_EL3(x0) +1: +2: + ret +3: + LoadConstantToReg(FixedPcdGet32(PcdCounterFrequency), x0) + msr cntfrq_el0, x0 + + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), x0) + ldrh w0, [x0] + ret diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf new file mode 100644 index 0000000..e09d940 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbLib.inf @@ -0,0 +1,56 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = LS1043aRdbLib + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OpenPlatformPkg/Platforms/Nxp/LS1043aRdb/LS1043aRdbPkg.dec + +[LibraryClasses] + IoLib + ArmLib + MemoryAllocationLib + I2cLib + DdrLib + SocLib + +[Sources.common] + LS1043aRdbHelper.S | GCC + LS1043aRdb.c + LS1043aRdbMem.c + Common.c + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmPlatformTokenSpaceGuid.PcdCounterFrequency diff --git a/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c new file mode 100644 index 0000000..ef93623 --- /dev/null +++ b/Platforms/Nxp/LS1043aRdb/Library/LS1043aRdbLib/LS1043aRdbMem.c @@ -0,0 +1,149 @@ +/** LS1043aRdbMem.c +* +* RDB memory specific Library for LS1043A SoC. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#include <Library/PlatformLib.h> + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_CCSR_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // OCRAM1 Space + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_OCRAM1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_OCRAM1_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_OCRAM1_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // OCRAM2 Space + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_OCRAM2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_OCRAM2_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_OCRAM2_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // IFC region 1 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_IFC_REGION1_BASE_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_BMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_IFC_REGION2_BASE_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_DRAM2_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP1_BASE_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP2_BASE_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_PCI_EXP3_BASE_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase = LS1043A_DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].Length = LS1043A_DRAM3_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +}