Add some registers configuration in PcieRasInitDxe and add PCIe local RAS interrupt handle in trusted firmware to support PCIe local RAS.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang ming.huang@linaro.org Reviewed-by: Leif Lindholm leif.lindholm@linaro.org --- Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi | Bin 21248 -> 22048 bytes Platform/Hisilicon/D06/bl1.bin | Bin 12432 -> 12432 bytes Platform/Hisilicon/D06/fip.bin | Bin 113450 -> 121866 bytes 3 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi b/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi index 0e22237..f9ceff2 100644 Binary files a/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.efi differ diff --git a/Platform/Hisilicon/D06/bl1.bin b/Platform/Hisilicon/D06/bl1.bin index 416535f..d0970e5 100644 Binary files a/Platform/Hisilicon/D06/bl1.bin and b/Platform/Hisilicon/D06/bl1.bin differ diff --git a/Platform/Hisilicon/D06/fip.bin b/Platform/Hisilicon/D06/fip.bin index c9b7ca0..795cfb5 100644 Binary files a/Platform/Hisilicon/D06/fip.bin and b/Platform/Hisilicon/D06/fip.bin differ